?? hdb3.tan.qmsg
字號:
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register insertv:inst\|count0\[16\] register insertv:inst\|count0\[2\] 221.39 MHz 4.517 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 221.39 MHz between source register \"insertv:inst\|count0\[16\]\" and destination register \"insertv:inst\|count0\[2\]\" (period= 4.517 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.373 ns + Longest register register " "Info: + Longest register to register delay is 4.373 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns insertv:inst\|count0\[16\] 1 REG LC_X34_Y8_N0 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X34_Y8_N0; Fanout = 4; REG Node = 'insertv:inst\|count0\[16\]'" { } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "" { insertv:inst|count0[16] } "NODE_NAME" } } { "insertv.vhd" "" { Text "E:/Quartus II/HDB3/insertv.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.573 ns) + CELL(0.366 ns) 0.939 ns insertv:inst\|Equal0~357 2 COMB LC_X35_Y8_N2 1 " "Info: 2: + IC(0.573 ns) + CELL(0.366 ns) = 0.939 ns; Loc. = LC_X35_Y8_N2; Fanout = 1; COMB Node = 'insertv:inst\|Equal0~357'" { } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "0.939 ns" { insertv:inst|count0[16] insertv:inst|Equal0~357 } "NODE_NAME" } } { "insertv.vhd" "" { Text "E:/Quartus II/HDB3/insertv.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.067 ns) + CELL(0.075 ns) 2.081 ns insertv:inst\|Equal0~361 3 COMB LC_X34_Y7_N7 3 " "Info: 3: + IC(1.067 ns) + CELL(0.075 ns) = 2.081 ns; Loc. = LC_X34_Y7_N7; Fanout = 3; COMB Node = 'insertv:inst\|Equal0~361'" { } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "1.142 ns" { insertv:inst|Equal0~357 insertv:inst|Equal0~361 } "NODE_NAME" } } { "insertv.vhd" "" { Text "E:/Quartus II/HDB3/insertv.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.336 ns) + CELL(0.183 ns) 2.600 ns insertv:inst\|count0\[29\]~595 4 COMB LC_X34_Y7_N9 32 " "Info: 4: + IC(0.336 ns) + CELL(0.183 ns) = 2.600 ns; Loc. = LC_X34_Y7_N9; Fanout = 32; COMB Node = 'insertv:inst\|count0\[29\]~595'" { } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "0.519 ns" { insertv:inst|Equal0~361 insertv:inst|count0[29]~595 } "NODE_NAME" } } { "insertv.vhd" "" { Text "E:/Quartus II/HDB3/insertv.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.012 ns) + CELL(0.761 ns) 4.373 ns insertv:inst\|count0\[2\] 5 REG LC_X34_Y10_N6 4 " "Info: 5: + IC(1.012 ns) + CELL(0.761 ns) = 4.373 ns; Loc. = LC_X34_Y10_N6; Fanout = 4; REG Node = 'insertv:inst\|count0\[2\]'" { } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "1.773 ns" { insertv:inst|count0[29]~595 insertv:inst|count0[2] } "NODE_NAME" } } { "insertv.vhd" "" { Text "E:/Quartus II/HDB3/insertv.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.385 ns ( 31.67 % ) " "Info: Total cell delay = 1.385 ns ( 31.67 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.988 ns ( 68.33 % ) " "Info: Total interconnect delay = 2.988 ns ( 68.33 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "4.373 ns" { insertv:inst|count0[16] insertv:inst|Equal0~357 insertv:inst|Equal0~361 insertv:inst|count0[29]~595 insertv:inst|count0[2] } "NODE_NAME" } } { "d:/program files/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii/win/Technology_Viewer.qrui" "4.373 ns" { insertv:inst|count0[16] insertv:inst|Equal0~357 insertv:inst|Equal0~361 insertv:inst|count0[29]~595 insertv:inst|count0[2] } { 0.000ns 0.573ns 1.067ns 0.336ns 1.012ns } { 0.000ns 0.366ns 0.075ns 0.183ns 0.761ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.022 ns - Smallest " "Info: - Smallest clock skew is 0.022 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.978 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 2.978 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns CLK 1 CLK PIN_M20 48 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 48; CLK Node = 'CLK'" { } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "HDB3.bdf" "" { Schematic "E:/Quartus II/HDB3/HDB3.bdf" { { 136 8 176 152 "CLK" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.608 ns) + CELL(0.542 ns) 2.978 ns insertv:inst\|count0\[2\] 2 REG LC_X34_Y10_N6 4 " "Info: 2: + IC(1.608 ns) + CELL(0.542 ns) = 2.978 ns; Loc. = LC_X34_Y10_N6; Fanout = 4; REG Node = 'insertv:inst\|count0\[2\]'" { } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "2.150 ns" { CLK insertv:inst|count0[2] } "NODE_NAME" } } { "insertv.vhd" "" { Text "E:/Quartus II/HDB3/insertv.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 46.00 % ) " "Info: Total cell delay = 1.370 ns ( 46.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.608 ns ( 54.00 % ) " "Info: Total interconnect delay = 1.608 ns ( 54.00 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "2.978 ns" { CLK insertv:inst|count0[2] } "NODE_NAME" } } { "d:/program files/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii/win/Technology_Viewer.qrui" "2.978 ns" { CLK CLK~out0 insertv:inst|count0[2] } { 0.000ns 0.000ns 1.608ns } { 0.000ns 0.828ns 0.542ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.956 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 2.956 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns CLK 1 CLK PIN_M20 48 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 48; CLK Node = 'CLK'" { } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "HDB3.bdf" "" { Schematic "E:/Quartus II/HDB3/HDB3.bdf" { { 136 8 176 152 "CLK" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.586 ns) + CELL(0.542 ns) 2.956 ns insertv:inst\|count0\[16\] 2 REG LC_X34_Y8_N0 4 " "Info: 2: + IC(1.586 ns) + CELL(0.542 ns) = 2.956 ns; Loc. = LC_X34_Y8_N0; Fanout = 4; REG Node = 'insertv:inst\|count0\[16\]'" { } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "2.128 ns" { CLK insertv:inst|count0[16] } "NODE_NAME" } } { "insertv.vhd" "" { Text "E:/Quartus II/HDB3/insertv.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 46.35 % ) " "Info: Total cell delay = 1.370 ns ( 46.35 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.586 ns ( 53.65 % ) " "Info: Total interconnect delay = 1.586 ns ( 53.65 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "2.956 ns" { CLK insertv:inst|count0[16] } "NODE_NAME" } } { "d:/program files/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii/win/Technology_Viewer.qrui" "2.956 ns" { CLK CLK~out0 insertv:inst|count0[16] } { 0.000ns 0.000ns 1.586ns } { 0.000ns 0.828ns 0.542ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "2.978 ns" { CLK insertv:inst|count0[2] } "NODE_NAME" } } { "d:/program files/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii/win/Technology_Viewer.qrui" "2.978 ns" { CLK CLK~out0 insertv:inst|count0[2] } { 0.000ns 0.000ns 1.608ns } { 0.000ns 0.828ns 0.542ns } } } { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "2.956 ns" { CLK insertv:inst|count0[16] } "NODE_NAME" } } { "d:/program files/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii/win/Technology_Viewer.qrui" "2.956 ns" { CLK CLK~out0 insertv:inst|count0[16] } { 0.000ns 0.000ns 1.586ns } { 0.000ns 0.828ns 0.542ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" { } { { "insertv.vhd" "" { Text "E:/Quartus II/HDB3/insertv.vhd" 16 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" { } { { "insertv.vhd" "" { Text "E:/Quartus II/HDB3/insertv.vhd" 16 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "4.373 ns" { insertv:inst|count0[16] insertv:inst|Equal0~357 insertv:inst|Equal0~361 insertv:inst|count0[29]~595 insertv:inst|count0[2] } "NODE_NAME" } } { "d:/program files/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii/win/Technology_Viewer.qrui" "4.373 ns" { insertv:inst|count0[16] insertv:inst|Equal0~357 insertv:inst|Equal0~361 insertv:inst|count0[29]~595 insertv:inst|count0[2] } { 0.000ns 0.573ns 1.067ns 0.336ns 1.012ns } { 0.000ns 0.366ns 0.075ns 0.183ns 0.761ns } } } { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "2.978 ns" { CLK insertv:inst|count0[2] } "NODE_NAME" } } { "d:/program files/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii/win/Technology_Viewer.qrui" "2.978 ns" { CLK CLK~out0 insertv:inst|count0[2] } { 0.000ns 0.000ns 1.608ns } { 0.000ns 0.828ns 0.542ns } } } { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "2.956 ns" { CLK insertv:inst|count0[16] } "NODE_NAME" } } { "d:/program files/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii/win/Technology_Viewer.qrui" "2.956 ns" { CLK CLK~out0 insertv:inst|count0[16] } { 0.000ns 0.000ns 1.586ns } { 0.000ns 0.828ns 0.542ns } } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "insertv:inst\|count0\[2\] CLR CLK 4.211 ns register " "Info: tsu for register \"insertv:inst\|count0\[2\]\" (data pin = \"CLR\", clock pin = \"CLK\") is 4.211 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.179 ns + Longest pin register " "Info: + Longest pin to register delay is 7.179 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns CLR 1 PIN PIN_U9 3 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_U9; Fanout = 3; PIN Node = 'CLR'" { } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "" { CLR } "NODE_NAME" } } { "HDB3.bdf" "" { Schematic "E:/Quartus II/HDB3/HDB3.bdf" { { 224 8 176 240 "CLR" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.953 ns) + CELL(0.366 ns) 5.406 ns insertv:inst\|count0\[29\]~595 2 COMB LC_X34_Y7_N9 32 " "Info: 2: + IC(3.953 ns) + CELL(0.366 ns) = 5.406 ns; Loc. = LC_X34_Y7_N9; Fanout = 32; COMB Node = 'insertv:inst\|count0\[29\]~595'" { } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "4.319 ns" { CLR insertv:inst|count0[29]~595 } "NODE_NAME" } } { "insertv.vhd" "" { Text "E:/Quartus II/HDB3/insertv.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.012 ns) + CELL(0.761 ns) 7.179 ns insertv:inst\|count0\[2\] 3 REG LC_X34_Y10_N6 4 " "Info: 3: + IC(1.012 ns) + CELL(0.761 ns) = 7.179 ns; Loc. = LC_X34_Y10_N6; Fanout = 4; REG Node = 'insertv:inst\|count0\[2\]'" { } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "1.773 ns" { insertv:inst|count0[29]~595 insertv:inst|count0[2] } "NODE_NAME" } } { "insertv.vhd" "" { Text "E:/Quartus II/HDB3/insertv.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.214 ns ( 30.84 % ) " "Info: Total cell delay = 2.214 ns ( 30.84 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.965 ns ( 69.16 % ) " "Info: Total interconnect delay = 4.965 ns ( 69.16 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "7.179 ns" { CLR insertv:inst|count0[29]~595 insertv:inst|count0[2] } "NODE_NAME" } } { "d:/program files/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii/win/Technology_Viewer.qrui" "7.179 ns" { CLR CLR~out0 insertv:inst|count0[29]~595 insertv:inst|count0[2] } { 0.000ns 0.000ns 3.953ns 1.012ns } { 0.000ns 1.087ns 0.366ns 0.761ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" { } { { "insertv.vhd" "" { Text "E:/Quartus II/HDB3/insertv.vhd" 16 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.978 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 2.978 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns CLK 1 CLK PIN_M20 48 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 48; CLK Node = 'CLK'" { } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "HDB3.bdf" "" { Schematic "E:/Quartus II/HDB3/HDB3.bdf" { { 136 8 176 152 "CLK" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.608 ns) + CELL(0.542 ns) 2.978 ns insertv:inst\|count0\[2\] 2 REG LC_X34_Y10_N6 4 " "Info: 2: + IC(1.608 ns) + CELL(0.542 ns) = 2.978 ns; Loc. = LC_X34_Y10_N6; Fanout = 4; REG Node = 'insertv:inst\|count0\[2\]'" { } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "2.150 ns" { CLK insertv:inst|count0[2] } "NODE_NAME" } } { "insertv.vhd" "" { Text "E:/Quartus II/HDB3/insertv.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 46.00 % ) " "Info: Total cell delay = 1.370 ns ( 46.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.608 ns ( 54.00 % ) " "Info: Total interconnect delay = 1.608 ns ( 54.00 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "2.978 ns" { CLK insertv:inst|count0[2] } "NODE_NAME" } } { "d:/program files/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii/win/Technology_Viewer.qrui" "2.978 ns" { CLK CLK~out0 insertv:inst|count0[2] } { 0.000ns 0.000ns 1.608ns } { 0.000ns 0.828ns 0.542ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "7.179 ns" { CLR insertv:inst|count0[29]~595 insertv:inst|count0[2] } "NODE_NAME" } } { "d:/program files/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii/win/Technology_Viewer.qrui" "7.179 ns" { CLR CLR~out0 insertv:inst|count0[29]~595 insertv:inst|count0[2] } { 0.000ns 0.000ns 3.953ns 1.012ns } { 0.000ns 1.087ns 0.366ns 0.761ns } } } { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "2.978 ns" { CLK insertv:inst|count0[2] } "NODE_NAME" } } { "d:/program files/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii/win/Technology_Viewer.qrui" "2.978 ns" { CLK CLK~out0 insertv:inst|count0[2] } { 0.000ns 0.000ns 1.608ns } { 0.000ns 0.828ns 0.542ns } } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK HDB3\[0\] codeout:inst2\|code\[0\] 7.167 ns register " "Info: tco from clock \"CLK\" to destination pin \"HDB3\[0\]\" through register \"codeout:inst2\|code\[0\]\" is 7.167 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.977 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 2.977 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns CLK 1 CLK PIN_M20 48 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 48; CLK Node = 'CLK'" { } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "HDB3.bdf" "" { Schematic "E:/Quartus II/HDB3/HDB3.bdf" { { 136 8 176 152 "CLK" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.607 ns) + CELL(0.542 ns) 2.977 ns codeout:inst2\|code\[0\] 2 REG LC_X35_Y6_N8 1 " "Info: 2: + IC(1.607 ns) + CELL(0.542 ns) = 2.977 ns; Loc. = LC_X35_Y6_N8; Fanout = 1; REG Node = 'codeout:inst2\|code\[0\]'" { } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "2.149 ns" { CLK codeout:inst2|code[0] } "NODE_NAME" } } { "codeout.vhd" "" { Text "E:/Quartus II/HDB3/codeout.vhd" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 46.02 % ) " "Info: Total cell delay = 1.370 ns ( 46.02 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.607 ns ( 53.98 % ) " "Info: Total interconnect delay = 1.607 ns ( 53.98 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "2.977 ns" { CLK codeout:inst2|code[0] } "NODE_NAME" } } { "d:/program files/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii/win/Technology_Viewer.qrui" "2.977 ns" { CLK CLK~out0 codeout:inst2|code[0] } { 0.000ns 0.000ns 1.607ns } { 0.000ns 0.828ns 0.542ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" { } { { "codeout.vhd" "" { Text "E:/Quartus II/HDB3/codeout.vhd" 18 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.034 ns + Longest register pin " "Info: + Longest register to pin delay is 4.034 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns codeout:inst2\|code\[0\] 1 REG LC_X35_Y6_N8 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X35_Y6_N8; Fanout = 1; REG Node = 'codeout:inst2\|code\[0\]'" { } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "" { codeout:inst2|code[0] } "NODE_NAME" } } { "codeout.vhd" "" { Text "E:/Quartus II/HDB3/codeout.vhd" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.630 ns) + CELL(2.404 ns) 4.034 ns HDB3\[0\] 2 PIN PIN_P8 0 " "Info: 2: + IC(1.630 ns) + CELL(2.404 ns) = 4.034 ns; Loc. = PIN_P8; Fanout = 0; PIN Node = 'HDB3\[0\]'" { } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "4.034 ns" { codeout:inst2|code[0] HDB3[0] } "NODE_NAME" } } { "HDB3.bdf" "" { Schematic "E:/Quartus II/HDB3/HDB3.bdf" { { 176 848 1024 192 "HDB3\[1..0\]" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.404 ns ( 59.59 % ) " "Info: Total cell delay = 2.404 ns ( 59.59 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.630 ns ( 40.41 % ) " "Info: Total interconnect delay = 1.630 ns ( 40.41 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "4.034 ns" { codeout:inst2|code[0] HDB3[0] } "NODE_NAME" } } { "d:/program files/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii/win/Technology_Viewer.qrui" "4.034 ns" { codeout:inst2|code[0] HDB3[0] } { 0.000ns 1.630ns } { 0.000ns 2.404ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "2.977 ns" { CLK codeout:inst2|code[0] } "NODE_NAME" } } { "d:/program files/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii/win/Technology_Viewer.qrui" "2.977 ns" { CLK CLK~out0 codeout:inst2|code[0] } { 0.000ns 0.000ns 1.607ns } { 0.000ns 0.828ns 0.542ns } } } { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "4.034 ns" { codeout:inst2|code[0] HDB3[0] } "NODE_NAME" } } { "d:/program files/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii/win/Technology_Viewer.qrui" "4.034 ns" { codeout:inst2|code[0] HDB3[0] } { 0.000ns 1.630ns } { 0.000ns 2.404ns } } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "insertv:inst\|codeoutv\[1\] datain CLK -2.303 ns register " "Info: th for register \"insertv:inst\|codeoutv\[1\]\" (data pin = \"datain\", clock pin = \"CLK\") is -2.303 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.977 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 2.977 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns CLK 1 CLK PIN_M20 48 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 48; CLK Node = 'CLK'" { } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "HDB3.bdf" "" { Schematic "E:/Quartus II/HDB3/HDB3.bdf" { { 136 8 176 152 "CLK" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.607 ns) + CELL(0.542 ns) 2.977 ns insertv:inst\|codeoutv\[1\] 2 REG LC_X34_Y6_N5 6 " "Info: 2: + IC(1.607 ns) + CELL(0.542 ns) = 2.977 ns; Loc. = LC_X34_Y6_N5; Fanout = 6; REG Node = 'insertv:inst\|codeoutv\[1\]'" { } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "2.149 ns" { CLK insertv:inst|codeoutv[1] } "NODE_NAME" } } { "insertv.vhd" "" { Text "E:/Quartus II/HDB3/insertv.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 46.02 % ) " "Info: Total cell delay = 1.370 ns ( 46.02 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.607 ns ( 53.98 % ) " "Info: Total interconnect delay = 1.607 ns ( 53.98 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "2.977 ns" { CLK insertv:inst|codeoutv[1] } "NODE_NAME" } } { "d:/program files/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii/win/Technology_Viewer.qrui" "2.977 ns" { CLK CLK~out0 insertv:inst|codeoutv[1] } { 0.000ns 0.000ns 1.607ns } { 0.000ns 0.828ns 0.542ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" { } { { "insertv.vhd" "" { Text "E:/Quartus II/HDB3/insertv.vhd" 16 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.380 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.380 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns datain 1 PIN PIN_T9 3 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_T9; Fanout = 3; PIN Node = 'datain'" { } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "" { datain } "NODE_NAME" } } { "HDB3.bdf" "" { Schematic "E:/Quartus II/HDB3/HDB3.bdf" { { 288 8 176 304 "datain" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.835 ns) + CELL(0.458 ns) 5.380 ns insertv:inst\|codeoutv\[1\] 2 REG LC_X34_Y6_N5 6 " "Info: 2: + IC(3.835 ns) + CELL(0.458 ns) = 5.380 ns; Loc. = LC_X34_Y6_N5; Fanout = 6; REG Node = 'insertv:inst\|codeoutv\[1\]'" { } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "4.293 ns" { datain insertv:inst|codeoutv[1] } "NODE_NAME" } } { "insertv.vhd" "" { Text "E:/Quartus II/HDB3/insertv.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.545 ns ( 28.72 % ) " "Info: Total cell delay = 1.545 ns ( 28.72 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.835 ns ( 71.28 % ) " "Info: Total interconnect delay = 3.835 ns ( 71.28 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "5.380 ns" { datain insertv:inst|codeoutv[1] } "NODE_NAME" } } { "d:/program files/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii/win/Technology_Viewer.qrui" "5.380 ns" { datain datain~out0 insertv:inst|codeoutv[1] } { 0.000ns 0.000ns 3.835ns } { 0.000ns 1.087ns 0.458ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "2.977 ns" { CLK insertv:inst|codeoutv[1] } "NODE_NAME" } } { "d:/program files/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii/win/Technology_Viewer.qrui" "2.977 ns" { CLK CLK~out0 insertv:inst|codeoutv[1] } { 0.000ns 0.000ns 1.607ns } { 0.000ns 0.828ns 0.542ns } } } { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "5.380 ns" { datain insertv:inst|codeoutv[1] } "NODE_NAME" } } { "d:/program files/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii/win/Technology_Viewer.qrui" "5.380 ns" { datain datain~out0 insertv:inst|codeoutv[1] } { 0.000ns 0.000ns 3.835ns } { 0.000ns 1.087ns 0.458ns } } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
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