{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Web Edition " "Info: Version 6.0 Build 178 04/27/2006 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Apr 02 18:43:23 2009 " "Info: Processing started: Thu Apr 02 18:43:23 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off HDB3 -c HDB3 " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off HDB3 -c HDB3" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IMPP_MPP_AUTO_ASSIGNED_DEVICE" "HDB3 EP1S10F484C5 " "Info: Automatically selected device EP1S10F484C5 for design HDB3" {  } {  } 0 0 "Automatically selected device %2!s! for design %1!s!" 0 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" {  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0}
{ "Info" "IFIOMGR_PINS_MISSING_LOCATION_INFO" "5 5 " "Info: No exact pin location assignment(s) for 5 pins of 5 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "HDB3\[1\] " "Info: Pin HDB3\[1\] not assigned to an exact location on the device" {  } { { "HDB3.bdf" "" { Schematic "E:/Quartus II/HDB3/HDB3.bdf" { { 176 848 1024 192 "HDB3\[1..0\]" "" } } } } { "d:/program files/quartus ii/win/Assignment Editor.qase" "" { Assignment "d:/program files/quartus ii/win/Assignment Editor.qase" 1 { { 0 "HDB3\[1\]" } } } } { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "" { HDB3[1] } "NODE_NAME" } } { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "" { HDB3[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "HDB3\[0\] " "Info: Pin HDB3\[0\] not assigned to an exact location on the device" {  } { { "HDB3.bdf" "" { Schematic "E:/Quartus II/HDB3/HDB3.bdf" { { 176 848 1024 192 "HDB3\[1..0\]" "" } } } } { "d:/program files/quartus ii/win/Assignment Editor.qase" "" { Assignment "d:/program files/quartus ii/win/Assignment Editor.qase" 1 { { 0 "HDB3\[0\]" } } } } { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "" { HDB3[0] } "NODE_NAME" } } { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "" { HDB3[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "CLK " "Info: Pin CLK not assigned to an exact location on the device" {  } { { "HDB3.bdf" "" { Schematic "E:/Quartus II/HDB3/HDB3.bdf" { { 136 8 176 152 "CLK" "" } } } } { "d:/program files/quartus ii/win/Assignment Editor.qase" "" { Assignment "d:/program files/quartus ii/win/Assignment Editor.qase" 1 { { 0 "CLK" } } } } { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "CLR " "Info: Pin CLR not assigned to an exact location on the device" {  } { { "HDB3.bdf" "" { Schematic "E:/Quartus II/HDB3/HDB3.bdf" { { 224 8 176 240 "CLR" "" } } } } { "d:/program files/quartus ii/win/Assignment Editor.qase" "" { Assignment "d:/program files/quartus ii/win/Assignment Editor.qase" 1 { { 0 "CLR" } } } } { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "" { CLR } "NODE_NAME" } } { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "" { CLR } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "datain " "Info: Pin datain not assigned to an exact location on the device" {  } { { "HDB3.bdf" "" { Schematic "E:/Quartus II/HDB3/HDB3.bdf" { { 288 8 176 304 "datain" "" } } } } { "d:/program files/quartus ii/win/Assignment Editor.qase" "" { Assignment "d:/program files/quartus ii/win/Assignment Editor.qase" 1 { { 0 "datain" } } } } { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "" { datain } "NODE_NAME" } } { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "" { datain } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0}  } {  } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0}
{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." {  } {  } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "CLK Global clock in PIN M20 " "Info: Automatically promoted signal \"CLK\" to use Global clock in PIN M20" {  } { { "HDB3.bdf" "" { Schematic "E:/Quartus II/HDB3/HDB3.bdf" { { 136 8 176 152 "CLK" "" } } } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 1 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 1 0}
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Extra Info: Start inferring scan chains for DSP blocks" {  } {  } 1 0 "Start inferring scan chains for DSP blocks" 1 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Extra Info: Inferring scan chains for DSP blocks is complete" {  } {  } 1 0 "Inferring scan chains for DSP blocks is complete" 1 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0 0 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0}
{ "Extra Info" "IFSAC_FSAC_START_LUT_IO_MAC_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, LUTs, RAM blocks, and DSP blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, LUTs, RAM blocks, and DSP blocks to improve timing and density" 1 0}