library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity insertv is
  port( clk  :  in  std_logic;
        clr  :  in  std_logic;
     codein  :  in  std_logic;
     codeoutv : out std_logic_vector(1 downto 0));
end;
 
architecture one of insertv is
  signal count0 : integer:=0;
   begin
 process(clk,clr)
   begin
  if clk'event and clk='1' then
     if clr='1' then 
        codeoutv<="00";count0<=0;
     else
        case codein is
           when '1'=>codeoutv<="01";count0<=0;
           when '0'=>if(count0=3) then 
                        codeoutv<="11";count0<=0;
                     else
                        count0<=count0+1;codeoutv<="00";
                     end if;
           when others=>codeoutv<="00";count0<=count0;
        end case;
      end if;
   end if;
 end process;
end;