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library ieee;
use ieee.std_logic_1164.all;

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entity fen is
port (clk:in std_logic;
     clk1:out std_logic);
end fen;

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architecture fen_arc of fen is
begin
     process (clk)
       variable cnt : integer range 0 to 120;
    begin 
     if clk'event and clk='1' then  ---輸入時鐘頻率12kHz，
                 if cnt=120 then
                       cnt:=0;      ---120個時鐘頻率記一次數
                       clk1<='1';   ---輸出時鐘頻率為100Hz
                else
                cnt:=cnt+1;
                clk1<='0';
                end if ;
     end if ;
   end process ;
end fen_arc ;