-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--clk_2 is clk_2 at LC3
clk_2_reg_input = VCC;
clk_2 = TFFE(clk_2_reg_input, GLOBAL(clk), , , );


--b4 is b4 at LC5
b4_or_out = m[3];
b4_reg_input = b4_or_out;
b4 = DFFE(b4_reg_input, GLOBAL(clk), , , );


--A1L23 is clk~6 at LC19
A1L23_or_out = clk;
A1L23 = A1L23_or_out;


--clk_4 is clk_4 at LC21
clk_4_reg_input = VCC;
clk_4 = TFFE(clk_4_reg_input, GLOBAL(clk), , , clk_2);


--b5 is b5 at LC11
b5_or_out = b4;
b5_reg_input = b5_or_out;
b5 = DFFE(b5_reg_input, GLOBAL(clk), , , );


--add_count[0] is add_count[0] at LC1
add_count[0]_or_out = !add_count[0];
add_count[0]_reg_input = add_count[0]_or_out;
add_count[0] = DFFE(add_count[0]_reg_input, GLOBAL(clk), , , );


--A1L5Q is A6~reg0 at LC13
A1L5Q_or_out = add_count[0];
A1L5Q_reg_input = A1L5Q_or_out;
A1L5Q = DFFE(A1L5Q_reg_input, GLOBAL(clk), , , );


--m[6] is m[6] at LC7
m[6]_or_out = b5;
m[6]_reg_input = m[6]_or_out;
m[6] = DFFE(m[6]_reg_input, GLOBAL(clk), , , );


--m[0] is m[0] at LC2
m[0]_p1_out = !m[3] & !b1 & !b2 & !b5 & !m[0] & !m[6];
m[0]_or_out = m[0]_p1_out # b4;
m[0]_reg_input = m[0]_or_out;
m[0] = TFFE(m[0]_reg_input, GLOBAL(clk), , , );


--b1 is b1 at LC16
b1_or_out = m[0];
b1_reg_input = b1_or_out;
b1 = DFFE(b1_reg_input, GLOBAL(clk), , , );


--b2 is b2 at LC14
b2_or_out = b1;
b2_reg_input = b2_or_out;
b2 = DFFE(b2_reg_input, GLOBAL(clk), , , );


--m[3] is m[3] at LC8
m[3]_or_out = b2;
m[3]_reg_input = m[3]_or_out;
m[3] = DFFE(m[3]_reg_input, GLOBAL(clk), , , );


--A1L28 is m[3]~98 at LC6
A1L28_or_out = m[3];
A1L28 = A1L28_or_out;


--add_count[1] is add_count[1] at LC4
add_count[1]_p1_out = !add_count[0] & m[6];
add_count[1]_p2_out = add_count[0] & !m[6];
add_count[1]_or_out = add_count[1]_p1_out # add_count[1]_p2_out;
add_count[1]_reg_input = !add_count[1]_or_out;
add_count[1] = TFFE(add_count[1]_reg_input, GLOBAL(clk), , , );


--A1L7Q is A7~reg0 at LC17
A1L7Q_or_out = add_count[1];
A1L7Q_reg_input = A1L7Q_or_out;
A1L7Q = DFFE(A1L7Q_reg_input, GLOBAL(clk), , , );


--clk is clk at PIN_83
--operation mode is input

clk = INPUT();


--A4 is A4 at PIN_12
--operation mode is output

A4 = OUTPUT(clk_2);


--A5 is A5 at PIN_21
--operation mode is output

A5 = OUTPUT(A1L23);


--A11 is A11 at PIN_11
--operation mode is output

A11 = OUTPUT(b4);


--A3 is A3 at PIN_20
--operation mode is output

A3 = OUTPUT(clk_4);


--A12 is A12 at PIN_8
--operation mode is output

A12 = OUTPUT(b5);


--A6 is A6 at PIN_6
--operation mode is output

A6 = OUTPUT(A1L5Q);


--A8 is A8 at PIN_4
--operation mode is output

A8 = OUTPUT(b1);


--A9 is A9 at PIN_5
--operation mode is output

A9 = OUTPUT(b2);


--data is data at PIN_9
--operation mode is output

data = OUTPUT(m[3]);


--A10 is A10 at PIN_10
--operation mode is output

A10 = OUTPUT(A1L28);


--A7 is A7 at PIN_22
--operation mode is output

A7 = OUTPUT(A1L7Q);