; alt_mercury_add_sub.inc          ; yes             ; Other           ; c:/altera/quartus51/libraries/megafunctions/alt_mercury_add_sub.inc ;
; aglobal51.inc                    ; yes             ; Other           ; c:/altera/quartus51/libraries/megafunctions/aglobal51.inc           ;
; addcore.tdf                      ; yes             ; Megafunction    ; c:/altera/quartus51/libraries/megafunctions/addcore.tdf             ;
; a_csnbuffer.inc                  ; yes             ; Other           ; c:/altera/quartus51/libraries/megafunctions/a_csnbuffer.inc         ;
; a_csnbuffer.tdf                  ; yes             ; Megafunction    ; c:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf         ;
; altshift.tdf                     ; yes             ; Megafunction    ; c:/altera/quartus51/libraries/megafunctions/altshift.tdf            ;
+----------------------------------+-----------------+-----------------+---------------------------------------------------------------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------+----------------------+
; Resource             ; Usage                ;
+----------------------+----------------------+
; Logic cells          ; 15                   ;
; Total registers      ; 13                   ;
; I/O pins             ; 12                   ;
; Maximum fan-out node ; clk                  ;
; Maximum fan-out      ; 14                   ;
; Total fan-out        ; 45                   ;
; Average fan-out      ; 1.67                 ;
+----------------------+----------------------+


+----------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                  ;
+----------------------------+------------+------+---------------------+
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ;
+----------------------------+------------+------+---------------------+
; |GMSK                      ; 15         ; 12   ; |GMSK               ;
+----------------------------+------------+------+---------------------+


+------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_add_sub:add_rtl_0 ;
+------------------------+-------------+---------------------------------+
; Parameter Name         ; Value       ; Type                            ;
+------------------------+-------------+---------------------------------+
; LPM_WIDTH              ; 2           ; Untyped                         ;
; LPM_REPRESENTATION     ; UNSIGNED    ; Untyped                         ;
; LPM_DIRECTION          ; DEFAULT     ; Untyped                         ;
; ONE_INPUT_IS_CONSTANT  ; YES         ; Untyped                         ;
; LPM_PIPELINE           ; 0           ; Untyped                         ;
; MAXIMIZE_SPEED         ; 5           ; Untyped                         ;
; REGISTERED_AT_END      ; 0           ; Untyped                         ;
; OPTIMIZE_FOR_SPEED     ; 9           ; Untyped                         ;
; USE_CS_BUFFERS         ; 1           ; Untyped                         ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                         ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH              ;
; DEVICE_FAMILY          ; MAX7000S    ; Untyped                         ;
; USE_WYS                ; OFF         ; Untyped                         ;
; STYLE                  ; FAST        ; Untyped                         ;
; CBXI_PARAMETER         ; add_sub_qag ; Untyped                         ;
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                      ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                    ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                    ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                  ;
+------------------------+-------------+---------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in C:/Documents and Settings/Administrator/桌面/VHDL/GMSK.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Tue Mar 17 12:16:43 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GMSK -c GMSK
Info: Found 2 design units, including 1 entities, in source file GMSK.vhd
    Info: Found design unit 1: GMSK-address
    Info: Found entity 1: GMSK
Info: Elaborating entity "GMSK" for the top level hierarchy
Info: Found 1 design units, including 1 entities, in source file ../../../../altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Found 1 design units, including 1 entities, in source file ../../../../altera/quartus51/libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Found 1 design units, including 1 entities, in source file ../../../../altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Found 1 design units, including 1 entities, in source file ../../../../altera/quartus51/libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Info: Duplicate registers merged to single register
    Info: Duplicate register "count_4" merged to single register "clk_2"
    Info: Duplicate register "m[1]" merged to single register "b1"
    Info: Duplicate register "m[2]" merged to single register "b2"
    Info: Duplicate register "b3" merged to single register "m[3]"
    Info: Duplicate register "m[4]" merged to single register "b4"
    Info: Duplicate register "m[5]" merged to single register "b5"
    Info: Duplicate register "b6" merged to single register "m[6]"
Info: Promoted pin-driven signal(s) to global signal
    Info: Promoted clock signal driven by pin "clk" to global clock signal
Info: Implemented 27 device resources after synthesis - the final resource count might be different
    Info: Implemented 1 input pins
    Info: Implemented 11 output pins
    Info: Implemented 15 macrocells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Processing ended: Tue Mar 17 12:16:45 2009
    Info: Elapsed time: 00:00:02