; Slack ; Required tco ; Actual tco ; From    ; To   ; From Clock ;
+-------+--------------+------------+---------+------+------------+
; N/A   ; None         ; 17.000 ns  ; m[3]    ; A10  ; clk        ;
; N/A   ; None         ; 8.000 ns   ; A7~reg0 ; A7   ; clk        ;
; N/A   ; None         ; 8.000 ns   ; m[3]    ; data ; clk        ;
; N/A   ; None         ; 8.000 ns   ; b2      ; A9   ; clk        ;
; N/A   ; None         ; 8.000 ns   ; b1      ; A8   ; clk        ;
; N/A   ; None         ; 8.000 ns   ; A6~reg0 ; A6   ; clk        ;
; N/A   ; None         ; 8.000 ns   ; b5      ; A12  ; clk        ;
; N/A   ; None         ; 8.000 ns   ; clk_4   ; A3   ; clk        ;
; N/A   ; None         ; 8.000 ns   ; b4      ; A11  ; clk        ;
; N/A   ; None         ; 8.000 ns   ; clk_2   ; A4   ; clk        ;
+-------+--------------+------------+---------+------+------------+


+---------------------------------------------------------+
; tpd                                                     ;
+-------+-------------------+-----------------+------+----+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+----+
; N/A   ; None              ; 15.000 ns       ; clk  ; A5 ;
+-------+-------------------+-----------------+------+----+


+---------------------------------------------------------------------------------+
; Minimum tco                                                                     ;
+---------------+------------------+----------------+---------+------+------------+
; Minimum Slack ; Required Min tco ; Actual Min tco ; From    ; To   ; From Clock ;
+---------------+------------------+----------------+---------+------+------------+
; N/A           ; None             ; 8.000 ns       ; clk_2   ; A4   ; clk        ;
; N/A           ; None             ; 8.000 ns       ; b4      ; A11  ; clk        ;
; N/A           ; None             ; 8.000 ns       ; clk_4   ; A3   ; clk        ;
; N/A           ; None             ; 8.000 ns       ; b5      ; A12  ; clk        ;
; N/A           ; None             ; 8.000 ns       ; A6~reg0 ; A6   ; clk        ;
; N/A           ; None             ; 8.000 ns       ; b1      ; A8   ; clk        ;
; N/A           ; None             ; 8.000 ns       ; b2      ; A9   ; clk        ;
; N/A           ; None             ; 8.000 ns       ; m[3]    ; data ; clk        ;
; N/A           ; None             ; 8.000 ns       ; A7~reg0 ; A7   ; clk        ;
; N/A           ; None             ; 17.000 ns      ; m[3]    ; A10  ; clk        ;
+---------------+------------------+----------------+---------+------+------------+


+-----------------------------------------------------------------+
; Minimum tpd                                                     ;
+---------------+-------------------+-----------------+------+----+
; Minimum Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+---------------+-------------------+-----------------+------+----+
; N/A           ; None              ; 15.000 ns       ; clk  ; A5 ;
+---------------+-------------------+-----------------+------+----+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Tue Mar 17 12:16:56 2009
Info: Command: quartus_tan --read_settings_files=on --write_settings_files=off GMSK -c GMSK --speed=15
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 76.92 MHz between source register "add_count[1]" and destination register "A7~reg0" (period= 13.0 ns)
    Info: + Longest register to register delay is 8.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4; Fanout = 2; REG Node = 'add_count[1]'
        Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC17; Fanout = 1; REG Node = 'A7~reg0'
        Info: Total cell delay = 6.000 ns ( 75.00 % )
        Info: Total interconnect delay = 2.000 ns ( 25.00 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 3.000 ns
            Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 14; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC17; Fanout = 1; REG Node = 'A7~reg0'
            Info: Total cell delay = 3.000 ns ( 100.00 % )
        Info: - Longest clock path from clock "clk" to source register is 3.000 ns
            Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 14; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC4; Fanout = 2; REG Node = 'add_count[1]'
            Info: Total cell delay = 3.000 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Micro setup delay of destination is 4.000 ns
Info: tco from clock "clk" to destination pin "A10" through register "m[3]" is 17.000 ns
    Info: + Longest clock path from clock "clk" to source register is 3.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 14; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC8; Fanout = 4; REG Node = 'm[3]'
        Info: Total cell delay = 3.000 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Longest register to pin delay is 13.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8; Fanout = 4; REG Node = 'm[3]'
        Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 9.000 ns; Loc. = LC6; Fanout = 1; COMB Node = 'm[3]~98'
        Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 13.000 ns; Loc. = PIN_10; Fanout = 0; PIN Node = 'A10'
        Info: Total cell delay = 11.000 ns ( 84.62 % )
        Info: Total interconnect delay = 2.000 ns ( 15.38 % )
Info: Longest tpd from source pin "clk" to destination pin "A5" is 15.000 ns
    Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 14; CLK Node = 'clk'
    Info: 2: + IC(1.000 ns) + CELL(7.000 ns) = 11.000 ns; Loc. = LC19; Fanout = 1; COMB Node = 'clk~6'
    Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 15.000 ns; Loc. = PIN_21; Fanout = 0; PIN Node = 'A5'
    Info: Total cell delay = 14.000 ns ( 93.33 % )
    Info: Total interconnect delay = 1.000 ns ( 6.67 % )
Info: Minimum tco from clock "clk" to destination pin "A4" through register "clk_2" is 8.000 ns
    Info: + Shortest clock path from clock "clk" to source register is 3.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 14; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC3; Fanout = 3; REG Node = 'clk_2'
        Info: Total cell delay = 3.000 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Shortest register to pin delay is 4.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3; Fanout = 3; REG Node = 'clk_2'
        Info: 2: + IC(0.000 ns) + CELL(4.000 ns) = 4.000 ns; Loc. = PIN_12; Fanout = 0; PIN Node = 'A4'
        Info: Total cell delay = 4.000 ns ( 100.00 % )
Info: Shortest tpd from source pin "clk" to destination pin "A5" is 15.000 ns
    Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 14; CLK Node = 'clk'
    Info: 2: + IC(1.000 ns) + CELL(7.000 ns) = 11.000 ns; Loc. = LC19; Fanout = 1; COMB Node = 'clk~6'
    Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 15.000 ns; Loc. = PIN_21; Fanout = 0; PIN Node = 'A5'
    Info: Total cell delay = 14.000 ns ( 93.33 % )
    Info: Total interconnect delay = 1.000 ns ( 6.67 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Tue Mar 17 12:16:57 2009
    Info: Elapsed time: 00:00:01