library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity GMSK is
port(
clk:in std_logic;
data:out std_logic;
A3:out std_logic;
A4:out std_logic;
A5:out std_logic;
A6:out std_logic;
A7:out std_logic;
A8:out std_logic;
A9:out std_logic;
A10:out std_logic;
A11:out std_logic;
A12:out std_logic
);
end GMSK;

architecture address of GMSK is
signal count_4:integer range 0 to 1;
signal clk_2:std_logic;
signal clk_4:std_logic;
signal b1,b2,b3,b4,b5,b6:std_logic;
signal add_count:integer range 0 to 3;
signal m:std_logic_vector(6 downto 0);

begin
process(clk)
begin

if(clk'event and clk='1') then
    
    m<=(m(5 downto 0)&(m(4) xor m(0) xor(not(m(6)or m(5)or m(4)or m(3)or m(2)or m(1)or m(0)))));
    --生成m序列 k=7
    clk_2<=not clk_2;   --二分頻
	
	if(count_4=1) then  --四分頻
    clk_4<=not clk_4; count_4<=0;
	else
    count_4<=count_4+1; 
	end if;
		
	b1<=m(0);
	b2<=b1;
	b3<=b2;
	b4<=b3;
	b5<=b4;
	b6<=b5;
	
	if(b6='1') then
		add_count<=add_count+1;
	else
		add_count<=add_count-1;
	end if;
	case add_count is           --象限數(shù)決定A6、A7
		when 0=>A6<='0';A7<='0';
		when 1=>A6<='1';A7<='0';
		when 2=>A6<='0';A7<='1';
		when 3=>A6<='1';A7<='1';
	end case;
end if;
end process;
data<=b3;
A3<=clk_4;
A4<=clk_2;
A5<=clk;
A8<=b1;
A9<=b2;
A10<=b3;
A11<=b4;
A12<=b5;
end address;