{ "Warning" "WTAN_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" {  } {  } 0 0 "Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "GMSK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL/GMSK.vhd" 7 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register add_count\[1\] register A7~reg0 76.92 MHz 13.0 ns Internal " "Info: Clock \"clk\" has Internal fmax of 76.92 MHz between source register \"add_count\[1\]\" and destination register \"A7~reg0\" (period= 13.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.000 ns + Longest register register " "Info: + Longest register to register delay is 8.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns add_count\[1\] 1 REG LC4 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4; Fanout = 2; REG Node = 'add_count\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "GMSK" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/VHDL/db/GMSK.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/VHDL/" "" "" { add_count[1] } "NODE_NAME" } "" } } { "GMSK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL/GMSK.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns A7~reg0 2 REG LC17 1 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC17; Fanout = 1; REG Node = 'A7~reg0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "GMSK" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/VHDL/db/GMSK.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/VHDL/" "" "8.000 ns" { add_count[1] A7~reg0 } "NODE_NAME" } "" } } { "GMSK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL/GMSK.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.000 ns ( 75.00 % ) " "Info: Total cell delay = 6.000 ns ( 75.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 25.00 % ) " "Info: Total interconnect delay = 2.000 ns ( 25.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "GMSK" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/VHDL/db/GMSK.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/VHDL/" "" "8.000 ns" { add_count[1] A7~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.000 ns" { add_count[1] A7~reg0 } { 0.000ns 2.000ns } { 0.000ns 6.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.000 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 14 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 14; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "GMSK" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/VHDL/db/GMSK.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/VHDL/" "" "" { clk } "NODE_NAME" } "" } } { "GMSK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL/GMSK.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns A7~reg0 2 REG LC17 1 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC17; Fanout = 1; REG Node = 'A7~reg0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "GMSK" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/VHDL/db/GMSK.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/VHDL/" "" "0.000 ns" { clk A7~reg0 } "NODE_NAME" } "" } } { "GMSK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL/GMSK.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 100.00 % ) " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "GMSK" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/VHDL/db/GMSK.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/VHDL/" "" "3.000 ns" { clk A7~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out A7~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.000 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 14 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 14; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "GMSK" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/VHDL/db/GMSK.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/VHDL/" "" "" { clk } "NODE_NAME" } "" } } { "GMSK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL/GMSK.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns add_count\[1\] 2 REG LC4 2 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC4; Fanout = 2; REG Node = 'add_count\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "GMSK" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/VHDL/db/GMSK.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/VHDL/" "" "0.000 ns" { clk add_count[1] } "NODE_NAME" } "" } } { "GMSK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL/GMSK.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 100.00 % ) " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "GMSK" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/VHDL/db/GMSK.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/VHDL/" "" "3.000 ns" { clk add_count[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out add_count[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "GMSK" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/VHDL/db/GMSK.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/VHDL/" "" "3.000 ns" { clk A7~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out A7~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "GMSK" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/VHDL/db/GMSK.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/VHDL/" "" "3.000 ns" { clk add_count[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out add_count[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "GMSK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL/GMSK.vhd" 34 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "GMSK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL/GMSK.vhd" 34 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "GMSK" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/VHDL/db/GMSK.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/VHDL/" "" "8.000 ns" { add_count[1] A7~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.000 ns" { add_count[1] A7~reg0 } { 0.000ns 2.000ns } { 0.000ns 6.000ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "GMSK" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/VHDL/db/GMSK.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/VHDL/" "" "3.000 ns" { clk A7~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out A7~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "GMSK" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/VHDL/db/GMSK.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/VHDL/" "" "3.000 ns" { clk add_count[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out add_count[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk A10 m\[3\] 17.000 ns register " "Info: tco from clock \"clk\" to destination pin \"A10\" through register \"m\[3\]\" is 17.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.000 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 14 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 14; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "GMSK" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/VHDL/db/GMSK.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/VHDL/" "" "" { clk } "NODE_NAME" } "" } } { "GMSK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL/GMSK.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns m\[3\] 2 REG LC8 4 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC8; Fanout = 4; REG Node = 'm\[3\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "GMSK" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/VHDL/db/GMSK.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/VHDL/" "" "0.000 ns" { clk m[3] } "NODE_NAME" } "" } } { "GMSK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL/GMSK.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 100.00 % ) " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "GMSK" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/VHDL/db/GMSK.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/VHDL/" "" "3.000 ns" { clk m[3] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out m[3] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "GMSK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL/GMSK.vhd" 34 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.000 ns + Longest register pin " "Info: + Longest register to pin delay is 13.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns m\[3\] 1 REG LC8 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8; Fanout = 4; REG Node = 'm\[3\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "GMSK" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/VHDL/db/GMSK.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/VHDL/" "" "" { m[3] } "NODE_NAME" } "" } } { "GMSK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL/GMSK.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 9.000 ns m\[3\]~98 2 COMB LC6 1 " "Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 9.000 ns; Loc. = LC6; Fanout = 1; COMB Node = 'm\[3\]~98'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "GMSK" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/VHDL/db/GMSK.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/VHDL/" "" "9.000 ns" { m[3] m[3]~98 } "NODE_NAME" } "" } } { "GMSK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL/GMSK.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 13.000 ns A10 3 PIN PIN_10 0 " "Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 13.000 ns; Loc. = PIN_10; Fanout = 0; PIN Node = 'A10'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "GMSK" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/VHDL/db/GMSK.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/VHDL/" "" "4.000 ns" { m[3]~98 A10 } "NODE_NAME" } "" } } { "GMSK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL/GMSK.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.000 ns ( 84.62 % ) " "Info: Total cell delay = 11.000 ns ( 84.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 15.38 % ) " "Info: Total interconnect delay = 2.000 ns ( 15.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "GMSK" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/VHDL/db/GMSK.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/VHDL/" "" "13.000 ns" { m[3] m[3]~98 A10 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "13.000 ns" { m[3] m[3]~98 A10 } { 0.000ns 2.000ns 0.000ns } { 0.000ns 7.000ns 4.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "GMSK" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/VHDL/db/GMSK.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/VHDL/" "" "3.000 ns" { clk m[3] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out m[3] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "GMSK" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/VHDL/db/GMSK.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/VHDL/" "" "13.000 ns" { m[3] m[3]~98 A10 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "13.000 ns" { m[3] m[3]~98 A10 } { 0.000ns 2.000ns 0.000ns } { 0.000ns 7.000ns 4.000ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "clk A5 15.000 ns Longest " "Info: Longest tpd from source pin \"clk\" to destination pin \"A5\" is 15.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 14 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 14; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "GMSK" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/VHDL/db/GMSK.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/VHDL/" "" "" { clk } "NODE_NAME" } "" } } { "GMSK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL/GMSK.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 11.000 ns clk~6 2 COMB LC19 1 " "Info: 2: + IC(1.000 ns) + CELL(7.000 ns) = 11.000 ns; Loc. = LC19; Fanout = 1; COMB Node = 'clk~6'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "GMSK" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/VHDL/db/GMSK.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/VHDL/" "" "8.000 ns" { clk clk~6 } "NODE_NAME" } "" } } { "GMSK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL/GMSK.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 15.000 ns A5 3 PIN PIN_21 0 " "Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 15.000 ns; Loc. = PIN_21; Fanout = 0; PIN Node = 'A5'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "GMSK" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/VHDL/db/GMSK.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/VHDL/" "" "4.000 ns" { clk~6 A5 } "NODE_NAME" } "" } } { "GMSK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/VHDL/GMSK.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "14.000 ns ( 93.33 % ) " "Info: Total cell delay = 14.000 ns ( 93.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 6.67 % ) " "Info: Total interconnect delay = 1.000 ns ( 6.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "GMSK" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/VHDL/db/GMSK.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/VHDL/" "" "15.000 ns" { clk clk~6 A5 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "15.000 ns" { clk clk~out clk~6 A5 } { 0.000ns 0.000ns 1.000ns 0.000ns } { 0.000ns 3.000ns 7.000ns 4.000ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}