?? csl_dpll.h
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/** @mainpage DPLL CSL 3.x * * @section Introduction * * @subsection xxx Purpose and Scope * The purpose of this document is to identify a set of common CSL APIs for the * DPLL module across various devices. The CSL developer is expected to refer to * this document while designing APIs for these modules. Some of the listed APIs * may not be applicable to a given DPLL module. While in other cases this list * of APIs may not be sufficient to cover all the features of a particular DPLL * Module. The CSL developer should use his discretion in designing new APIs or * extending the existing ones to cover these. * * @subsection aaa Terms and Abbreviations * -# CSL: Chip Support Library * -# API: Application Programmer Interface * * @subsection References * -# CSL-001-DES, CSL 3.x Design Specification DocumentVersion 1.02 * *//** @file csl_dpll.h * * @brief Header file for functional layer of CSL * * Description * - The different enumerations, structure definitions * and function declarations * * Modification 1 * - modified on: 30/01/2004 * - reason: Created the sources * * @date 30th Jan, 2004 * @author Amruth Tadas. */#ifndef _CSL_DPLL_H_#define _CSL_DPLL_H_#ifdef __cplusplusextern "C" {#endif#include <csl.h>#include <cslr_dpll.h>/**************************************************************************\* DPLL global typedef declarations\**************************************************************************//** @brief Enumeration for the Test mode */typedef enum { /** Disable Test Mode */ CSL_DPLL_TEST_OFF = 0, /** Enable Test Mode */ CSL_DPLL_TEST_ON = 1}CSL_DpllTest;/** @brief Enumeration for setting the DPLL mode. */typedef enum { /** Set the DPLL mode to BYPASS */ CSL_DPLL_MODE_BYPASS = 0, /** Set the DPLL mode to PLL */ CSL_DPLL_MODE_LOCK = 1}CSL_DpllMode;/** @brief Enumeration for the Initialize of Break setting */typedef enum { /** Disable Initialize on Break */ CSL_DPLL_IOB_OFF = 0, /** Enable Initialize on Break */ CSL_DPLL_IOB_ON = 1}CSL_DpllIob;/** @brief Enumeration for the line break status information. */typedef enum { /** DPLL has broken lock */ CSL_DPLL_LINE_BREAK = 0, /** DPLL Lock has been restored or write to control register has occurred */ CSL_DPLL_LINE_NOBREAK = 1}CSL_DpllLine;/** @brief Enumeration for the lock status information */ typedef enum { /** DPLL is NOT in Locked Mode */ CSL_DPLL_LOCK_OFF = 0, /** DPLL is in Locked Mode */ CSL_DPLL_LOCK_ON = 1}CSL_DpllLock;/** @brief Enumeration for the level shifter */ typedef enum { /** Level shifter in transparent Mode */ CSL_DPLL_LEVEL_TRANSPARENT_MODE = 0, /** Level shifter in isolated Mode */ CSL_DPLL_LEVEL_ISOLATED_MODE = 1}CSL_DpllLevel;/** @brief Enumeration for queries passed to @a CSL_dpllHwControl() * * This is used to select the commands to control the operations * existing setup of DPLL. The arguments to be passed with each * enumeration if any are specified next to the enumeration */typedef enum { /** Set the DPLL Mode : argument type @a CSL_DpllMode */ CSL_DPLL_CMD_SET_MODE = 1, /** Set the frequency of the o/p clock. The clock multiplier and divider are * passed as part of @ CSL_DpllHwSetup structure. * <b> Note:</b> Only pllmult, plldiv and bypassdiv are used in the * @a CSL_DpllHwSetup structure. In case of BYPASS MODE, only bypassdiv is used. * In case of LOCK MODE, both pllmult and plldiv are used. */ CSL_DPLL_CMD_SET_FREQ = 2} CSL_DpllHwControlCmd;/** @brief Enumeration for queries passed to @a CSL_dpllGetHwStatus() * * This is used to get the status of different operations or to get the * existing setup of DPLL. The status information is returned with argument * next to the enumeration */ typedef enum { /** Get the status of the Lock. */ CSL_DPLL_QUERY_LOCK_STATUS = 1, /** Get the DPLL mode. */ CSL_DPLL_QUERY_MODE_STATUS = 2, /** Get the break status */ CSL_DPLL_QUERY_BREAK_STATUS = 3} CSL_DpllHwStatusQuery ;/** * @brief The config-structure * * Used to configure the DPLL using CSL_dpllHwSetupRaw(..) */typedef struct { Uint16 CTL; /**< CTL register */} CSL_DpllConfig;/** * @brief Default values for the config-structure */#define CSL_DPLL_CONFIG_DEFAULTS { \ \ CSL_FMKT(DPLL_CTL_LS_DISABLE, RESETVAL) | \ CSL_FMKT(DPLL_CTL_IAI, RESETVAL) | \ CSL_FMKT(DPLL_CTL_IOB, RESETVAL) | \ CSL_FMKT(DPLL_CTL_TEST, RESETVAL) | \ CSL_FMKT(DPLL_CTL_PLL_MULT, RESETVAL) | \ CSL_FMKT(DPLL_CTL_PLL_DIV, RESETVAL) | \ CSL_FMKT(DPLL_CTL_PLL_ENABLE, RESETVAL) | \ CSL_FMKT(DPLL_CTL_BYPASS_DIV, RESETVAL) | \ CSL_FMKT(DPLL_CTL_BREAKLN, RESETVAL) | \ CSL_FMKT(DPLL_CTL_LOCK, RESETVAL) \}/** @brief This object contains the reference to the instance of DPLL opened * using the @a CSL_dpllOpen(). * * The pointer to this, is passed to all DPLL CSL APIs. */typedef struct CSL_DpllObj { /** This is a pointer to the registers of the instance of DPLL * referred to by this object */ CSL_DpllRegsOvly regs; /** This is the instance of DPLL being referred to by this object */ CSL_InstNum perNum;} CSL_DpllObj;typedef struct CSL_DpllObj *CSL_DpllHandle;/** @brief This will have the base-address information for the peripheral * instance */typedef struct { /** Base-address of the Configuration registers of the peripheral */ CSL_DpllRegsOvly regs;} CSL_DpllBaseAddress;/** @brief Module specific parameters. Present implementation doesn't have * any module specific parameters. */typedef struct{ /** Bit mask to be used for module specific parameters. * The below declaration is just a place-holder for future * implementation. */ CSL_BitMask16 flags;} CSL_DpllParam;/** @brief Module specific context information. Present implementation doesn't have * any Context information. */typedef struct { /** Context information of DPLL. * The below declaration is just a place-holder for future * implementation. */ Uint16 contextInfo;} CSL_DpllContext;/** @brief This has all the fields required to configure DPLL at Power Up * (After a Hardware Reset). * * This structure is used to setup or obtain the existing setup of * DPLL using @a CSL_dpllHwSetup() & @a CSL_dpllGetHwSetup() functions * respectively. */typedef struct CSL_DpllHwSetup { /** Level shifter. 1==>Level shifter in isolated mode, * 0==>Level shifter in transparent mode */ Uint16 ls_mode; /** Initialize on Break. 1==> Enable, 0==> Disable */ Uint16 iob; /** PLL or Bypass Mode 1==>LOCK mode, 0==>Bypass mode */ Uint16 pllMode; /** DPLL clock multiplier value in PLL mode. */ Uint16 pllmult; /** DPLL clock divider value in PLL mode. * The clockout will be clkref/(plldiv+1)(as per spec) */ Uint16 plldiv; /** DPLL clock divider value in Bypass mode. */ Uint16 bypassdiv; /** DPLL test/normal mode 1==>Test mode. 0==> Normal mode */ Uint16 test;}CSL_DpllHwSetup;/** * @brief Default values for the setup-parameters */#define CSL_DPLL_HWSETUP_DEFAULTS { \ /* .ls_mode = */ 0x0, \ /* .iob = */ 0x1, \ /* .pllMode = */ 0x1, \ /* .pllmult = */ 0x0, \ /* .plldiv = */ 0x0, \ /* .bypassdiv = */ 0x0, \ /* .test = */ 0x0 \}/**************************************************************************\* DPLL global function declarations\**************************************************************************//** @brief Peripheral specific initialization function. * * This is the peripheral specific intialization function. This function is * idempotent in that calling it many times is same as calling it once. * This function initializes the CSL data structures, and doesn't touches * the hardware. * * <b> Usage Constraints: </b> * This function should be called before using any of the CSL APIs in the DPLL * module. * * Note: As DPLL doesn't have any context based information, currently, the function * just returns CSL_SOK. User is expected to pass NULL in the function call. * * @b Example: * @verbatim ... if (CSL_SOK != CSL_dpllInit(NULL)) { return; } @endverbatim * * @return returns the status of the operation * */CSL_Status CSL_dpllInit( /** DPLL specific context information */ CSL_DpllContext * pContext );/** @brief Opens the instance of DPLL requested. * * The open call sets up the data structures for the particular instance of
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