`timescale 1ns / 1psmodule Rs232_Recv2(RxD_data,parity, RxD_data_ready, RxD_data_fetch, Clk, RxD);input Clk, RxD,RxD_data_fetch;output reg [7:0] RxD_data;output RxD_data_ready,parity;reg  RxD_ready_flag;assign RxD_data_ready= RxD_ready_flag && ~RxD_data_fetch;reg Baud8Tick;reg [5:0]BaudDivCnt;// Vamos a revisar 8 veces por ciclo a ver si viene un bicho// assign Baud8Tick = BaudDivCnt[5] && BaudDivCnt[4] && BaudDivCnt[2] && BaudDivCnt[0]; // 50M / 53 = casi cabe -cabe mas- 8 veces en 115200always @(negedge Clk)begin // if == 110101 reg baud=1; 	if (Baud8Tick)begin		BaudDivCnt <= 0;		Baud8Tick<= 0;		end	else if (BaudDivCnt == 6'b110101)		Baud8Tick <= 1;	else		BaudDivCnt <= BaudDivCnt + 1;endreg [1:0]buffer_in; always @(posedge Clk)if(Baud8Tick)	buffer_in <= {buffer_in[0],~RxD}; // Cola FIFO de llegada	// Aseguramos qeu sea un pulsoreg [1:0] loop;reg RxD_bit;// we invert RxD, so that the idle becomes "0", to prevent a phantom character to be received at startup <--- :D eso es!// No vei que al principio los rejishters son ziroalways@(posedge Clk)if(Baud8Tick) begin // Ojo que start bit = 0	if(buffer_in[1] && loop!=2'b11) loop <= loop +1; // Aca se espera un par de muestras	else	if(~buffer_in[1] && loop!=2'b00) loop <= loop -1;  if(loop==2'b00) RxD_bit <= 0;  else  if(loop==2'b11) RxD_bit <= 1;end reg[3:0] state;reg [2:0] bit_spacing;reg parity;wire next_bit = (bit_spacing==7);    // el otro bit viene al menos 7 tick despues ( 8 ticks por periodo)always@(posedge Clk)beginif(Baud8Tick) 	case(state)  4'b0000: if(RxD_bit) state <= 4'b1000; // start bit found?  4'b1000: if(next_bit) state <= 4'b1001; // bit 0  4'b1001: if(next_bit) state <= 4'b1010; // bit 1  4'b1010: if(next_bit) state <= 4'b1011; // bit 2  4'b1011: if(next_bit) state <= 4'b1100; // bit 3  4'b1100: if(next_bit) state <= 4'b1101; // bit 4  4'b1101: if(next_bit) state <= 4'b1110; // bit 5  4'b1110: if(next_bit) state <= 4'b1111; // bit 6  4'b1111: if(next_bit) state <= 4'b0011; // bit 7  4'b0011: if(next_bit) begin state <= 4'b0001; parity<= ~RxD_bit; end // parity  4'b0001: if(next_bit) begin state <= 4'b0000; RxD_ready_flag <=1; end  default: state <= 4'b0000;endcase if(RxD_data_fetch)  RxD_ready_flag <=0;endalways @(posedge Clk)if(state==0)  bit_spacing <= 0;elseif(Baud8Tick)  bit_spacing <= bit_spacing + 1;always @(posedge Clk) if(Baud8Tick && next_bit && state[3]) beginRxD_data <= {~RxD_bit, RxD_data[7:1]}; endendmodule