/*H**************************************************************************
* NAME:         mcu.h
*----------------------------------------------------------------------------
* Copyright (c) 2006 Atmel.
*----------------------------------------------------------------------------
* RELEASE:      at90usb128-demo-cdc-1_0_3
* REVISION:     1.6.6.9.2.21
*----------------------------------------------------------------------------
* PURPOSE:
* SFR Description file for AtmegaUSB.
*****************************************************************************/
#ifndef MCU_H
#define MCU_H

/*==========================*/
/* Predefined SFR Addresses */
/*==========================*/

/******************************************************************************/
#if defined(__ICCAVR__) || defined(__IAR_SYSTEMS_ASM__)
/******************************************************************************/
SFR_B(PINA,   0x00) /* Input Pins, Port A */
SFR_B(DDRA,   0x01) /* Data Direction Register, Port A */
SFR_B(PORTA,  0x02) /* Data Register, Port A */

SFR_B(PINB,   0x03) /* Input Pins, Port B */
SFR_B(DDRB,   0x04) /* Data Direction Register, Port B */
SFR_B(PORTB,  0x05) /* Data Register, Port B */

SFR_B(PINC,   0x06) /* Input Pins, Port C */
SFR_B(DDRC,   0x07) /* Data Direction Register, Port C */
SFR_B(PORTC,  0x08) /* Data Register, Port C */

SFR_B(PIND,   0x09) /* Input Pins, Port D */
SFR_B(DDRD,   0x0A) /* Data Direction Register, Port D */
SFR_B(PORTD,  0x0B) /* Data Register, Port D */

SFR_B(PINE,   0x0C) /* Input Pins, Port E */
SFR_B(DDRE,   0x0D) /* Data Direction Register, Port E */
SFR_B(PORTE,  0x0E) /* Data Register, Port E */

SFR_B(PINF,   0x0F) /* Input Pins, Port F */
SFR_B(DDRF,   0x10) /* Data Direction Register, Port F */
SFR_B(PORTF,  0x11) /* Data Register, Port F */

SFR_B(PING,   0x12) /* Input Pins, Port G */
SFR_B(DDRG,   0x13) /* Data Direction Register, Port G */
SFR_B(PORTG,  0x14) /* Data Register, Port G */

SFR_B(TIFR0,   0x15) /* Timer/Counter Interrupt Flag register 0*/
SFR_B(TIFR1,   0x16) /* Timer/Counter Interrupt Flag register 1*/
SFR_B(TIFR2,   0x17) /* Timer/Counter Interrupt Flag register 2*/
SFR_B(TIFR3,   0x18) /* Timer/Counter Interrupt Flag register 3*/

SFR_B(EIFR,   0x1C)     /* External Interrupt Flag Register */
SFR_B(EIMSK,  0x1D)     /* External Interrupt Mask Register */

SFR_B(GPIOR0,  0x1E)     /* General Purpose Register 0 */

SFR_B(EECR,   0x1F)     /* EEPROM Control Register */
SFR_B(EEDR,   0x20)     /* EEPROM Data Register */
SFR_W(EEAR,   0x21)     /* EEPROM Address Register */

SFR_B(GTCCR,  0x23)     /* General Purpose Register */

SFR_B(TCCR0A,  0x24)     /* Timer/Counter 0 Control Register */
SFR_B(TCNT0,   0x26)     /* Timer/Counter 0 */
SFR_B(OCR0A,   0x27)     /* Timer/Counter 0 Output Compare Register */

SFR_B(TCCR0B,  0x25)     /* Timer/Counter 0 Control Register B*/


SFR_B(GPIOR1,  0x2A)     /* General Purpose Register 1 */
SFR_B(GPIOR2,  0x2B)     /* General Purpose Register 2 */

SFR_B(SPCR,   0x2C)     /* SPI Control Register */
SFR_B(SPSR,   0x2D)     /* SPI Status Register */
SFR_B(SPDR,   0x2E)     /* SPI I/O Data Register */

SFR_B(ACSR,   0x30)     /* Analog Comparator Control and Status Register */

SFR_B(OCDR,   0x31)     /* On-Chip Debug Register */

SFR_B(SMCR,   0x33)    /* Sleep Mode Control Register */
SFR_B(MCUSR,  0x34)    /* MCU Status Register */
SFR_B(MCUCR,  0x35)    /* MCU Control Register */

SFR_B(SPMCSR, 0x37)     /* Store Program Memory Control and Status Register */

SFR_B(RAMPZ,  0x3B)     /* RAM Page Z Select Register */

SFR_W(SP,     0x3D)     /* Stack Pointer */
SFR_B(SREG,   0x3F)     /* Status Register */

SFR_B(PLLCSR,    0x29); /* PLL Control and Status Register*/

SFR_B_EXT(WDTCR,  0x60)     /* Watchdog Timer Control Register for compatibility*/
SFR_B_EXT(WDTCSR,  0x60)    /* Watchdog Timer Control Register */
SFR_B_EXT(CLKPR,  0x61)     /* Clock Prescale Register */
SFR_B_EXT(OSCCAL, 0x66)     /* Oscillator Calibration Register */

SFR_B_EXT(EICRA,  0x69)     /* External Interrupt Control Register A */
SFR_B_EXT(EICRB,  0x6A)     /* External Interrupt Control Register B */

SFR_B_EXT(TIMSK0,  0x6E)     /* Timer/Counter 0 Interrupt Mask Register */
SFR_B_EXT(TIMSK1,  0x6F)     /* Timer/Counter 1 Interrupt Mask Register */
SFR_B_EXT(TIMSK2,  0x70)     /* Timer/Counter 2 Interrupt Mask Register */
SFR_B_EXT(TIMSK3,  0x71)     /* Timer/Counter 3 Interrupt Mask Register */

SFR_B_EXT(XMCRA,  0x74)     /* External Memory Control Register A */
SFR_B_EXT(XMCRB,  0x75)     /* External Memory Control Register B */

SFR_W_EXT(ADC,    0x78)     /* ADC Data register */
SFR_B_EXT(ADCSRA, 0x7A)     /* ADC Control and Status Register A */
SFR_B_EXT(ADCSRB, 0x7B)     /* ADC Control and Status Register B */
SFR_B_EXT(ADMUX,  0x7C)     /* ADC Multiplexer Selection Register */

SFR_B_EXT(DIDR0,  0x7E)     /* Digital Input Disable Register 0 */
SFR_B_EXT(DIDR1,  0x7F)     /* Digital Input Disable Register 1 */

SFR_B_EXT(TCCR1A, 0x80)     /* Timer/Counter 1 Control Register A */
SFR_B_EXT(TCCR1B, 0x81)     /* Timer/Counter 1 Control Register B */
SFR_B_EXT(TCCR1C, 0x82)     /* Timer/Counter 1 Control Register C */
SFR_W_EXT(TCNT1,  0x84)     /* Timer/Counter 1 Register */
SFR_W_EXT(ICR1,   0x86)     /* Timer/Counter 1 Input Capture Register */
SFR_W_EXT(OCR1A,  0x88)     /* Timer/Counter 1 Output Compare Register A */
SFR_W_EXT(OCR1B,  0x8A)     /* Timer/Counter 1 Output Compare Register B */
SFR_W_EXT(OCR1C,  0x8C)     /* Timer/Counter 1 Output Compare Register C */

SFR_B_EXT(TCCR3A, 0x90)     /* Timer/Counter 3 Control Register A */
SFR_B_EXT(TCCR3B, 0x91)     /* Timer/Counter 3 Control Register B */
SFR_B_EXT(TCCR3C, 0x92)     /* Timer/Counter 3 Control Register C */
SFR_W_EXT(TCNT3,  0x94)     /* Timer/Counter 3 Register */
SFR_W_EXT(ICR3,   0x96)     /* Timer/Counter 3 Input Capture Register */
SFR_W_EXT(OCR3A,  0x98)     /* Timer/Counter 3 Output Compare Register A */
SFR_W_EXT(OCR3B,  0x9A)     /* Timer/Counter 3 Output Compare Register B */
SFR_W_EXT(OCR3C,  0x9C)     /* Timer/Counter 3 Output Compare Register C */

SFR_B_EXT(TCCR2A, 0xB0)     /* Timer/Counter 2 Control Register A */
SFR_B_EXT(TCCR2B, 0xB1)     /* Timer/Counter 2 Control Register A */
SFR_B_EXT(TCNT2,  0xB2)     /* Timer/Counter 2 Register */
SFR_B_EXT(OCR2A,  0xB3)     /* Timer/Counter 2 Output Compare Register A */

SFR_B_EXT(ASSR,   0xB6)     /* Asynchronous mode Status Register */

SFR_B_EXT(TWBR,   0xB8)     /* TWI Bit Rate Register */
SFR_B_EXT(TWSR,   0XB9)     /* TWI Status Register */
SFR_B_EXT(TWAR,   0xBA)     /* TWI Address Register */
SFR_B_EXT(TWDR,   0xBB)     /* TWI Data Register */
SFR_B_EXT(TWCR,   0xBC)     /* TWI Control Register */


SFR_B_EXT(UCSR1A, 0xC8)     /* USART1 Control and Status Register A */
SFR_B_EXT(UCSR1B, 0xC9)     /* USART1 Control and Status Register B */
SFR_B_EXT(UCSR1C, 0xCA)     /* USART1 Control and Status Register C */
SFR_W_EXT(UBRR1,  0xCC)     /* USART1 Baud Rate Register Low */
//SFR_B_EXT(UBRR1L, 0xCC)
//SFR_B_EXT(UBRR1H, 0xCD)
SFR_B_EXT(UDR1,   0xCE)     /* USART1 I/O Data Register */

SFR_B_EXT(PCICR, 0x68)      /* Pin Change interrupt enable */
SFR_B_EXT(PCIFR, 0x3B)      /* Pin Change interrupt flag*/
SFR_B_EXT(PCMSK0, 0x6B)     /* Pin Change interrupt mask */



// USB CONTROLLER
//USB Hardware configuration
SFR_B_EXT(UHWCON,    0xD7);

// USB General
// Page 1
SFR_B_EXT(USBCON,    0xD8);
SFR_B_EXT(USBSTA,    0xD9);
SFR_B_EXT(USBINT,    0xDA);
SFR_B_EXT(UDPADDH,   0xDC);
SFR_B_EXT(UDPADDL,   0xDB);
SFR_B_EXT(OTGCON,    0xDD);
SFR_B_EXT(OTGTCON,   0xF9);
SFR_B_EXT(OTGIEN,    0xDE);
SFR_B_EXT(OTGINT,    0xDF);

// USB Device
// Page 1
SFR_B_EXT(UDCON,     0xE0);
SFR_B_EXT(UDINT,     0xE1);
SFR_B_EXT(UDIEN,     0xE2);
SFR_B_EXT(UDADDR,    0xE3);
SFR_B_EXT(UDFNUMH,   0xE5);
SFR_B_EXT(UDFNUML,   0xE4);
SFR_B_EXT(UDMFN,     0xE6);
SFR_B_EXT(UDTST,     0xE7);

// USB Endpoint
// Page 1
SFR_B_EXT(UENUM,     0xE9);
SFR_B_EXT(UERST,     0xEA);
SFR_B_EXT(UECONX,    0xEB);
SFR_B_EXT(UECFG0X,   0xEC);
SFR_B_EXT(UECFG1X,   0xED);
SFR_B_EXT(UESTA0X,   0xEE);
SFR_B_EXT(UESTA1X,   0xEF);
SFR_B_EXT(UEINTX,    0xE8);
SFR_B_EXT(UEIENX,    0xF0);
SFR_B_EXT(UEDATX,    0xF1);
SFR_B_EXT(UEBCHX,    0xF3);
SFR_B_EXT(UEBCLX,    0xF2);
SFR_B_EXT(UEINT,     0xF4);

// USB Host
// Page 1
SFR_B_EXT(UHCON,     0x9E);
SFR_B_EXT(UHINT,     0x9F);
SFR_B_EXT(UHIEN,     0xA0);
SFR_B_EXT(UHADDR,    0xA1);
SFR_B_EXT(UHFNUMH,   0xA3);
SFR_B_EXT(UHFNUML,   0xA2);
SFR_B_EXT(UHFLEN,    0xA4);

// USB Pipe
// Page 1
SFR_B_EXT(UPNUM,     0xA7);
SFR_B_EXT(UPRST,     0xA8);
SFR_B_EXT(UPCONX,    0xA9);
SFR_B_EXT(UPCFG0X,   0xAA);
SFR_B_EXT(UPCFG1X,   0xAB);
SFR_B_EXT(UPCFG2X,   0xAD);
SFR_B_EXT(UPSTAX,    0xAC);
SFR_B_EXT(UPINRQX,   0xA5);
SFR_B_EXT(UPERRX,    0xF5);
SFR_B_EXT(UPINTX,    0xA6);
SFR_B_EXT(UPIENX,    0xAE);
SFR_B_EXT(UPDATX,    0xAF);
SFR_B_EXT(UPBCHX,    0xF7);
SFR_B_EXT(UPBCLX,    0xF6);
SFR_B_EXT(UPINT,     0xF8);



/*==============================*/
/* Interrupt Vector Definitions */
/*==============================*/
/* NB! vectors are specified as byte addresses */
#define    RESET_vect                  (0x00)
#define    INT0_vect                   (0x04)
#define    INT1_vect                   (0x08)
#define    INT2_vect                   (0x0C)
#define    INT3_vect                   (0x10)
#define    INT4_vect                   (0x14)
#define    INT5_vect                   (0x18)
#define    INT6_vect                   (0x1C)
#define    INT7_vect                   (0x20)
#define    PCINT0_vect		            (0x24)
#define    USB_GENERAL_vect            (0x28)
#define    USB_ENDPOINT_PIPE_vect      (0x2C)
#define    WDT_vect			            (0x30)
#define    TIMER2_COMPA_vect           (0x34)
#define    TIMER2_COMPB_vect           (0x38)
#define    TIMER2_OVF_vect             (0x3C)
#define    TIMER1_CAPT_vect            (0x40)
#define    TIMER1_COMPA_vect           (0x44)
#define    TIMER1_COMPB_vect           (0x48)
#define    TIMER1_COMPC_vect           (0x4C)
#define    TIMER1_OVF_vect             (0x50)
#define    TIMER0_COMPA_vect           (0x54)
#define    TIMER0_COMPB_vect           (0x58)
#define    TIMER0_OVF_vect             (0x5C)
#define    SPI_STC_vect                (0x60)
#define    USART1_RXC_vect             (0x64)
#define    USART1_UDRE_vect            (0x68)
#define    USART1_TXC_vect             (0x6C)
#define    ANA_COMP_vect               (0x70)
#define    ADC_vect                    (0x74)
#define    EE_RDY_vect                 (0x78)
#define    TIMER3_CAPT_vect            (0x7C)
#define    TIMER3_COMPA_vect           (0x80)
#define    TIMER3_COMPB_vect           (0x84)
#define    TIMER3_COMPC_vect           (0x88)
#define    TIMER3_OVF_vect             (0x8C)
#define    TWI_vect                    (0x90)
#define    SPM_RDY_vect                (0x94)

#endif /* _IAR_ */
/******************************************************************************/
#ifdef __CODEVISIONAVR__
/******************************************************************************/
#define PINA    (*(volatile unsigned char *)0x20)  /* Input Pins, Port A */
#define DDRA    (*(volatile unsigned char *)0x21) /* Data Direction Register, Port A */
#define PORTA   (*(volatile unsigned char *)0x22) /* Data Register, Port A */

#define PINB    (*(volatile unsigned char *)0x23) /* Input Pins, Port B */
#define DDRB    (*(volatile unsigned char *)0x24) /* Data Direction Register, Port B */
#define PORTB   (*(volatile unsigned char *)0x25) /* Data Register, Port B */

#define PINC    (*(volatile unsigned char *)0x26) /* Input Pins, Port C */
#define DDRC    (*(volatile unsigned char *)0x27) /* Data Direction Register, Port C */
#define PORTC   (*(volatile unsigned char *)0x28) /* Data Register, Port C */

#define PIND    (*(volatile unsigned char *)0x29) /* Input Pins, Port D */
#define DDRD    (*(volatile unsigned char *)0x2A) /* Data Direction Register, Port D */
#define PORTD   (*(volatile unsigned char *)0x2B) /* Data Register, Port D */

#define PINE    (*(volatile unsigned char *)0x2C) /* Input Pins, Port E */
#define DDRE    (*(volatile unsigned char *)0x2D) /* Data Direction Register, Port E */
#define PORTE   (*(volatile unsigned char *)0x2E) /* Data Register, Port E */

#define PINF    (*(volatile unsigned char *)0x2F) /* Input Pins, Port F */
#define DDRF    (*(volatile unsigned char *)0x30) /* Data Direction Register, Port F */
#define PORTF   (*(volatile unsigned char *)0x31) /* Data Register, Port F */

#define PING    (*(volatile unsigned char *)0x32) /* Input Pins, Port G */
#define DDRG    (*(volatile unsigned char *)0x33) /* Data Direction Register, Port G */
#define PORTG   (*(volatile unsigned char *)0x34) /* Data Register, Port G */

#define TIFR0   (*(volatile unsigned char *)0x35) /* Timer/Counter Interrupt Flag register 0*/
#define TIFR1   (*(volatile unsigned char *)0x36) /* Timer/Counter Interrupt Flag register 1*/
#define TIFR2   (*(volatile unsigned char *)0x37) /* Timer/Counter Interrupt Flag register 2*/
#define TIFR3   (*(volatile unsigned char *)0x38) /* Timer/Counter Interrupt Flag register 3*/

#define EIFR    (*(volatile unsigned char *)0x3C)     /* External Interrupt Flag Register */
#define EIMSK   (*(volatile unsigned char *)0x3D)     /* External Interrupt Mask Register */

#define GPIOR0  (*(volatile unsigned char *)0x3E)     /* General Purpose Register 0 */

#define EECR    (*(volatile unsigned char *)0x3F)     /* EEPROM Control Register */
#define EEDR    (*(volatile unsigned char *)0x40)     /* EEPROM Data Register */
#define EEAR    (*(volatile unsigned int *)0x41)     /* EEPROM Address Register */

#define GTCCR   (*(volatile unsigned char *)0x43)     /* General Purpose Register */

#define TCCR0A  (*(volatile unsigned char *)0x44)     /* Timer/Counter 0 Control Register */
#define TCNT0   (*(volatile unsigned char *)0x46)     /* Timer/Counter 0 */
#define OCR0A   (*(volatile unsigned char *)0x47)     /* Timer/Counter 0 Output Compare Register */

#define GPIOR1  (*(volatile unsigned char *)0x4A)     /* General Purpose Register 1 */
#define GPIOR2  (*(volatile unsigned char *)0x4B)     /* General Purpose Register 2 */

#define SPCR    (*(volatile unsigned char *)0x4C)     /* SPI Control Register */
#define SPSR    (*(volatile unsigned char *)0x4D)     /* SPI Status Register */
#define SPDR    (*(volatile unsigned char *)0x4E)     /* SPI I/O Data Register */

#define ACSR    (*(volatile unsigned char *)0x50)     /* Analog Comparator Control and Status Register */

#define OCDR    (*(volatile unsigned char *)0x51)     /* On-Chip Debug Register */

#define SMCR    (*(volatile unsigned char *)0x53)    /* Sleep Mode Control Register */
#define MCUSR   (*(volatile unsigned char *)0x53)    /* MCU Status Register */
#define MCUCR   (*(volatile unsigned char *)0x53)    /* MCU Control Register */

#define SPMCSR  (*(volatile unsigned char *)0x57)     /* Store Program Memory Control and Status Register */

#define RAMPZ   (*(volatile unsigned char *)0x5B)     /* RAM Page Z Select Register */

#define SP      (*(volatile unsigned int *)0x5D)     /* Stack Pointer */
#define SREG    (*(volatile unsigned char *)0x5F)     /* Status Register */

#define WDTCR   (*(volatile unsigned char *)0x60)     /* Watchdog Timer Control Register */
#define CLKPR   (*(volatile unsigned char *)0x61)     /* Clock Prescale Register */
#define OSCCAL  (*(volatile unsigned char *)0x66)     /* Oscillator Calibration Register */

#define EICRA   (*(volatile unsigned char *)0x69)     /* External Interrupt Control Register A */
#define EICRB   (*(volatile unsigned char *)0x6A)     /* External Interrupt Control Register B */

#define TIMSK0  (*(volatile unsigned char *)0x6E)     /* Timer/Counter 0 Interrupt Mask Register */
#define TIMSK1  (*(volatile unsigned char *)0x6F)     /* Timer/Counter 1 Interrupt Mask Register */
#define TIMSK2  (*(volatile unsigned char *)0x70)     /* Timer/Counter 2 Interrupt Mask Register */
#define TIMSK3  (*(volatile unsigned char *)0x71)     /* Timer/Counter 3 Interrupt Mask Register */

#define XMCRA   (*(volatile unsigned char *)0x74)     /* External Memory Control Register A */
#define XMCRB   (*(volatile unsigned char *)0x75)     /* External Memory Control Register B */

#define ADC     (*(volatile unsigned int *)0x78)     /* ADC Data register */
#define ADCSRA  (*(volatile unsigned char *)0x7A)     /* ADC Control and Status Register A */
#define ADCSRB  (*(volatile unsigned char *)0x7B)     /* ADC Control and Status Register B */
#define ADMUX   (*(volatile unsigned char *)0x7C)     /* ADC Multiplexer Selection Register */

#define DIDR0   (*(volatile unsigned char *)0x7E)     /* Digital Input Disable Register 0 */
#define DIDR1   (*(volatile unsigned char *)0x7F)     /* Digital Input Disable Register 1 */

#define TCCR1A  (*(volatile unsigned char *)0x80)     /* Timer/Counter 1 Control Register A */
#define TCCR1B  (*(volatile unsigned char *)0x81)     /* Timer/Counter 1 Control Register B */
#define TCCR1C  (*(volatile unsigned char *)0x82)     /* Timer/Counter 1 Control Register C */
#define TCNT1   (*(volatile unsigned int *)0x84)     /* Timer/Counter 1 Register */
#define ICR1    (*(volatile unsigned int *)0x86)     /* Timer/Counter 1 Input Capture Register */
#define OCR1A   (*(volatile unsigned int *)0x88)     /* Timer/Counter 1 Output Compare Register A */
#define OCR1B   (*(volatile unsigned int *)0x8A)     /* Timer/Counter 1 Output Compare Register B */
#define OCR1C   (*(volatile unsigned int *)0x8C)     /* Timer/Counter 1 Output Compare Register C */

#define TCCR3A  (*(volatile unsigned char *)0x90)     /* Timer/Counter 3 Control Register A */
#define TCCR3B  (*(volatile unsigned char *)0x91)     /* Timer/Counter 3 Control Register B */
#define TCCR3C  (*(volatile unsigned char *)0x92)     /* Timer/Counter 3 Control Register C */
#define TCNT3   (*(volatile unsigned int *)0x94)     /* Timer/Counter 3 Register */
#define ICR3    (*(volatile unsigned int *)0x96)     /* Timer/Counter 3 Input Capture Register */
#define OCR3A   (*(volatile unsigned int *)0x98)     /* Timer/Counter 3 Output Compare Register A */
#define OCR3B   (*(volatile unsigned int *)0x9A)     /* Timer/Counter 3 Output Compare Register B */
#define OCR3C   (*(volatile unsigned int *)0x9C)     /* Timer/Counter 3 Output Compare Register C */

#define TCCR2A  (*(volatile unsigned char *)0xB0)     /* Timer/Counter 2 Control Register A */
#define TCNT2   (*(volatile unsigned char *)0xB2)     /* Timer/Counter 2 Register */
#define OCR2A   (*(volatile unsigned char *)0xB3)     /* Timer/Counter 2 Output Compare Register A */

#define ASSR   (*(volatile unsigned char *)0xB6)     /* Asynchronous mode Status Register */