/******************************************************************************/
/* DMA.h                                                                    */
/*                                                                            */
/* This is proprietary information, not to be published -- DIGIPRO DATA   	  */
/* Copyright (C) 2002, DigiPro Information Co.,Ltd.  All Rights Reserved.     */
/*                                                                            */
/* Author: Wu DingMing                                                        */
/* Date: August 12, 2002                                                      */
/******************************************************************************/

/******************************************************************************/
/*	DMA Sub Registers				                                          */
/******************************************************************************/                                                                                
#define DMSRC0_SUBADDR          0x0000
#define DMDST0_SUBADDR          0x0001
#define DMCTR0_SUBADDR          0x0002
#define DMSFC0_SUBADDR          0x0003
#define DMMCR0_SUBADDR          0x0004
#define DMSRC1_SUBADDR          0x0005
#define DMDST1_SUBADDR          0x0006
#define DMCTR1_SUBADDR          0x0007
#define DMSFC1_SUBADDR          0x0008
#define DMMCR1_SUBADDR          0x0009
#define DMSRC2_SUBADDR          0x000a
#define DMDST2_SUBADDR          0x000b
#define DMCTR2_SUBADDR          0x000c
#define DMSFC2_SUBADDR          0x000d
#define DMMCR2_SUBADDR          0x000e
#define DMSRC3_SUBADDR          0x000f
#define DMDST3_SUBADDR          0x0010
#define DMCTR3_SUBADDR          0x0011
#define DMSFC3_SUBADDR          0x0012
#define DMMCR3_SUBADDR          0x0013
#define DMSRC4_SUBADDR          0x0014
#define DMDST4_SUBADDR          0x0015
#define DMCTR4_SUBADDR          0x0016
#define DMSFC4_SUBADDR          0x0017
#define DMMCR4_SUBADDR          0x0018
#define DMSRC5_SUBADDR          0x0019
#define DMDST5_SUBADDR          0x001a
#define DMCTR5_SUBADDR          0x001b
#define DMSFC5_SUBADDR          0x001c
#define DMMCR5_SUBADDR          0x001d
#define DMSRCP_SUBADDR          0x001e
#define DMDSTP_SUBADDR          0x001f
#define DMIDX0_SUBADDR          0x0020
#define DMIDX1_SUBADDR          0x0021
#define DMFRI0_SUBADDR          0x0022
#define DMFRI1_SUBADDR          0x0023
#define DMGSA_SUBADDR           0x0024
#define DMGDA_SUBADDR           0x0025
#define DMGCR_SUBADDR           0x0026
#define DMGFR_SUBADDR           0x0027
/******************************************************************************/
/* DMA Channel Priority and Enable Control Register(DMPREC) bits              */
/******************************************************************************/
/* +-0f-+-0e-+-0d--08-+-07-06-+--05-04--+									  */
/* |FREE|RSVD|  DPRC  |INTOSEL| DE[5:0] |									  */
/* +----+----+--------+-------+---------+									  */
/******************************************************************************/

/******************************************************************************/
/* DMA Sync Event and Frame Count Register(DMSFCn) bits						  */
/******************************************************************************/
/* +--0f-0c--+-0b-+-0a--08-+---07-00---+									  */
/* |DSYN[3:0]|DBLW|  RSVD  |Frame Count|									  */
/* +---------+----+--------+-----------+									  */
/******************************************************************************/    

/******************************************************************************/
/* DMA Transfer Mode Control Register(DMMCRn) bits							  */
/******************************************************************************/
/* +---0f---+-0e-+-0d-+-0c--+-0b-+-0a-08-+7-6+-05-+4--2+1-0+				  */
/* |AUTOINIT|DINM|IMOD|CTMOD|rsvd| SIND  |DMS|rsvd|DIND|DMD|				  */
/* +--------+----+----+-----+----+-------+---+----+----+---+				  */
/******************************************************************************/