library verilog;use verilog.vl_types.all;entity top is    port(        clk             : in     vl_logic;        reset           : in     vl_logic;        decode_out      : out    vl_logic;        rst_encode      : out    vl_logic;        en_encode       : out    vl_logic;        valid_out       : out    vl_logic;        result          : out    vl_logic;        result_valid    : out    vl_logic;        valid_data_result: out    vl_logic;        data_out_result : out    vl_logic;        valid_data_out_cnt40: out    vl_logic;        data_out_cnt40  : out    vl_logic;        valid_out_cnt25_temp: out    vl_logic;        valid_out_temp  : out    vl_logic    );end top;