?? dds.v
字號:
module DDS(data,we,clk,ce,reset,sine,cose); input [31:0] data; //????? input we; //???????? input clk; input ce; //DDS?? input reset; output [15:0] sine; //?????? output [15:0] cose; //?????? reg [31:0] ADD_A; //?????????????? reg [31:0] ADD_B; //?????????????? reg [15:0] cose_DR; //????????? reg [15:0] sine_DR; wire [31:0] data; wire [9:0] ROM_A; wire [15:0] cose_D; wire [15:0] sine_D; assign cose=cose_DR; assign sine=sine_DR; assign ROM_A=ADD_B[31:22]; always @(posedge clk or posedge reset) begin if(reset) ADD_A<=0; //????????????????0 else if(we) ADD_A<=data; end always @(posedge clk or posedge reset) begin if(reset) ADD_B<=0; else if(ce) ADD_B<=ADD_B+ADD_A; end always @(posedge clk or posedge reset) begin if(reset) cose_DR<=0; else if(ce) cose_DR<=cose_D; end always @(posedge clk or posedge reset) begin if(reset) sine_DR<=0; else if(ce) sine_DR<=sine_D; end //????ROM IP?????????????????? rom_cose cose1(.addra(ROM_A),.clka(clk),.douta(cose_D)); rom_sine sine1(.addra(ROM_A),.clka(clk),.douta(sine_D)); endmodule?? 快捷鍵說明
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