;******************************************************************************
;  MSP-FET430P140 Demo - I2C, Master Reads from MSP430 Slave, Repeat Mode
;
;  Description: This demo connects two MSP430's via the I2C bus. The master
;  reads from the slave in repeat mode. This is the master code. The slave
;  code is called fet140_i2c_09.s43. The data from the slave TX
;  begins at 0 and is incremented with each transfer. The received data is in
;  RXData and is checked for validity. If the received data is incorrect, the
;  CPU is trapped and the P1.0 LED will stay on. The RXRDYIFG interrupt is
;  used to know when new data has been received.
;  A Stop is issued after Master receives 6 bytes and then a new Start is
;  issued.
;  ACLK = n/a, MCLK = SMCLK = I2CCLOCK = DCO ~ 800kHz
;  //* MSP430F169 Device Required *//
;
;                                 /|\  /|\
;                  MSP430F169     10k  10k     MSP430F169
;                    slave         |    |        master
;              -----------------|  |    |  -----------------
;             |             P3.1|<-|---+->|P3.1             |
;             |                 |  |      |             P1.0|-->LED
;             |                 |  |      |                 |
;             |             P3.3|<-+----->|P3.3             |
;             |                 |         |                 |
;
;
;   H. Grewal/A. Dannenberg
;   Texas Instruments Inc.
;   Feb 2005
;   Built with IAR Embedded Workbench Version: 3.21A
;******************************************************************************
#include  <msp430x16x.h>
;------------------------------------------------------------------------------
            ORG     01100h                  ; Progam Start
;------------------------------------------------------------------------------
RESET       mov.w   #0A00h,SP               ; Initialize stackpointer
StopWDT     mov.w   #WDTPW+WDTHOLD,&WDTCTL  ; Stop WDT
            bis.b   #0Ah,&P3SEL             ; Select I2C pins
            bis.b   #01h,&P1DIR             ; P1.0 output
            bic.b   #01h,&P1OUT             ; Clear P1.0

I2C_init    bis.b   #I2C+SYNC,&U0CTL        ; Recommended init procedure
            bic.b   #I2CEN,&U0CTL           ; Recommended init procedure
            bis.b   #I2CSSEL1+I2CRM,&I2CTCTL; SMCLK,repeat Mode
            mov     #0048h,&I2CSA           ; Slave Address is 048h
            bis.b   #RXRDYIE,&I2CIE         ; Enable RXRDYIE
            bis.b   #I2CEN,&U0CTL           ; Enable I2C

            clr     R6                      ; Use R6 to check incoming data
            clr     R7                      ; check if 6 bytes rcvd

            eint                            ; Enable interrupts

            bis.b   #MST,&U0CTL             ; Master mode
            bis.b   #I2CSTT,&I2CTCTL        ; Initiate transfer
Mainloop    cmp     #06h,R7
            jnz     rptRX
            clr     R7
            inc.b   R6
            bis.b   #I2CSTP,&I2CTCTL        ; Issue STOP
chkSTP      bit.b   #I2CSTP,&I2CTCTL        ; Check STP condition
            jnz     chkSTP
            bis.b   #MST,&U0CTL             ; Master mode
            bis.b   #I2CSTT,&I2CTCTL        ; Initiate transfer
rptRX       inc.b   R7
            bis.b   #LPM0,SR                ; Enter LPM0
            bis.b   #01h,&P1OUT             ; Set P1.0
            cmp     R5,R6                   ; Test received data
            jne     Trap                    ; Trap CPU if wrong
            bic.b   #01h,&P1OUT             ; Clear P1.0
            inc.b   R6                      ; Increment correct RX value
            jmp     Mainloop                ; Repeat

Trap        jmp     $                       ; Trap CPU

;------------------------------------------------------------------------------
I2C_ISR;    Common ISR for I2C Module
;------------------------------------------------------------------------------
            add     &I2CIV,PC               ; Add I2C offset vector
            reti                            ; No interrupt
            reti                            ; Arbitration Lost
            reti                            ; No Acknowledge
            reti                            ; Own Address
            reti                            ; Register Access Ready
            jmp     RXRDY_ISR               ; Receive Ready
            reti                            ; Transmit Ready
            reti                            ; General Call
            reti                            ; Start Condition

RXRDY_ISR   mov.b   &I2CDRB,R5              ; RX data in R5
            bic     #LPM0,0(SP)             ; Clear LPM0
            reti

;------------------------------------------------------------------------------
;           Interrupt Vectors
;------------------------------------------------------------------------------
            ORG     0FFFEh                  ; MSP430 RESET vector
            DW      RESET                   ;
            ORG     0FFF0h                  ; I2C interruplt vector
            DW      I2C_ISR                 ;
            END