AT91_REG	 EMAC_HSL; 	/* Hash Address Low[31:0] */	AT91_REG	 EMAC_SA1L; 	/* Specific Address 1 Low, First 4 bytes */	AT91_REG	 EMAC_SA1H; 	/* Specific Address 1 High, Last 2 bytes */	AT91_REG	 EMAC_SA2L; 	/* Specific Address 2 Low, First 4 bytes */	AT91_REG	 EMAC_SA2H; 	/* Specific Address 2 High, Last 2 bytes */	AT91_REG	 EMAC_SA3L; 	/* Specific Address 3 Low, First 4 bytes */	AT91_REG	 EMAC_SA3H; 	/* Specific Address 3 High, Last 2 bytes */	AT91_REG	 EMAC_SA4L; 	/* Specific Address 4 Low, First 4 bytes */	AT91_REG	 EMAC_SA4H; 	/* Specific Address 4 High, Last 2 bytesr */} AT91S_EMAC, *AT91PS_EMAC;/* -------- EMAC_CTL : (EMAC Offset: 0x0)  --------  */#define AT91C_EMAC_LB		((unsigned int) 0x1 <<  0) /* (EMAC) Loopback. Optional. When set, loopback signal is at high level. */#define AT91C_EMAC_LBL		((unsigned int) 0x1 <<  1) /* (EMAC) Loopback local. */#define AT91C_EMAC_RE		((unsigned int) 0x1 <<  2) /* (EMAC) Receive enable. */#define AT91C_EMAC_TE		((unsigned int) 0x1 <<  3) /* (EMAC) Transmit enable. */#define AT91C_EMAC_MPE		((unsigned int) 0x1 <<  4) /* (EMAC) Management port enable. */#define AT91C_EMAC_CSR		((unsigned int) 0x1 <<  5) /* (EMAC) Clear statistics registers. */#define AT91C_EMAC_ISR		((unsigned int) 0x1 <<  6) /* (EMAC) Increment statistics registers. */#define AT91C_EMAC_WES		((unsigned int) 0x1 <<  7) /* (EMAC) Write enable for statistics registers. */#define AT91C_EMAC_BP		((unsigned int) 0x1 <<  8) /* (EMAC) Back pressure. *//* -------- EMAC_CFG : (EMAC Offset: 0x4) Network Configuration Register --------  */#define AT91C_EMAC_SPD		((unsigned int) 0x1 <<  0) /* (EMAC) Speed. */#define AT91C_EMAC_FD		((unsigned int) 0x1 <<  1) /* (EMAC) Full duplex. */#define AT91C_EMAC_BR		((unsigned int) 0x1 <<  2) /* (EMAC) Bit rate. */#define AT91C_EMAC_CAF		((unsigned int) 0x1 <<  4) /* (EMAC) Copy all frames. */#define AT91C_EMAC_NBC		((unsigned int) 0x1 <<  5) /* (EMAC) No broadcast. */#define AT91C_EMAC_MTI		((unsigned int) 0x1 <<  6) /* (EMAC) Multicast hash enable */#define AT91C_EMAC_UNI		((unsigned int) 0x1 <<  7) /* (EMAC) Unicast hash enable. */#define AT91C_EMAC_BIG		((unsigned int) 0x1 <<  8) /* (EMAC) Receive 1522 bytes. */#define AT91C_EMAC_EAE		((unsigned int) 0x1 <<  9) /* (EMAC) External address match enable. */#define AT91C_EMAC_CLK		((unsigned int) 0x3 << 10) /* (EMAC) */#define AT91C_EMAC_CLK_HCLK_8	((unsigned int) 0x0 << 10) /* (EMAC) HCLK divided by 8 */#define AT91C_EMAC_CLK_HCLK_16	((unsigned int) 0x1 << 10) /* (EMAC) HCLK divided by 16 */#define AT91C_EMAC_CLK_HCLK_32	((unsigned int) 0x2 << 10) /* (EMAC) HCLK divided by 32 */#define AT91C_EMAC_CLK_HCLK_64	((unsigned int) 0x3 << 10) /* (EMAC) HCLK divided by 64 */#define AT91C_EMAC_RTY		((unsigned int) 0x1 << 12) /* (EMAC) */#define AT91C_EMAC_RMII		((unsigned int) 0x1 << 13) /* (EMAC) *//* -------- EMAC_SR : (EMAC Offset: 0x8) Network Status Register --------  */#define AT91C_EMAC_MDIO		((unsigned int) 0x1 <<  1) /* (EMAC) */#define AT91C_EMAC_IDLE		((unsigned int) 0x1 <<  2) /* (EMAC) *//* -------- EMAC_TCR : (EMAC Offset: 0x10) Transmit Control Register -------- */#define AT91C_EMAC_LEN		((unsigned int) 0x7FF <<  0) /* (EMAC) */#define AT91C_EMAC_NCRC		((unsigned int) 0x1 << 15) /* (EMAC) *//* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Control Register -------- */#define AT91C_EMAC_OVR		((unsigned int) 0x1 <<  0) /* (EMAC) */#define AT91C_EMAC_COL		((unsigned int) 0x1 <<  1) /* (EMAC) */#define AT91C_EMAC_RLE		((unsigned int) 0x1 <<  2) /* (EMAC) */#define AT91C_EMAC_TXIDLE	((unsigned int) 0x1 <<  3) /* (EMAC) */#define AT91C_EMAC_BNQ		((unsigned int) 0x1 <<  4) /* (EMAC) */#define AT91C_EMAC_COMP		((unsigned int) 0x1 <<  5) /* (EMAC) */#define AT91C_EMAC_UND		((unsigned int) 0x1 <<  6) /* (EMAC) *//* -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- */#define AT91C_EMAC_BNA		((unsigned int) 0x1 <<  0) /* (EMAC) */#define AT91C_EMAC_REC		((unsigned int) 0x1 <<  1) /* (EMAC) */#define AT91C_EMAC_RSR_OVR	((unsigned int) 0x1 <<  2) /* (EMAC) *//* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- */#define AT91C_EMAC_DONE		((unsigned int) 0x1 <<  0) /* (EMAC) */#define AT91C_EMAC_RCOM		((unsigned int) 0x1 <<  1) /* (EMAC) */#define AT91C_EMAC_RBNA		((unsigned int) 0x1 <<  2) /* (EMAC) */#define AT91C_EMAC_TOVR		((unsigned int) 0x1 <<  3) /* (EMAC) */#define AT91C_EMAC_TUND		((unsigned int) 0x1 <<  4) /* (EMAC) */#define AT91C_EMAC_RTRY		((unsigned int) 0x1 <<  5) /* (EMAC) */#define AT91C_EMAC_TBRE		((unsigned int) 0x1 <<  6) /* (EMAC) */#define AT91C_EMAC_TCOM		((unsigned int) 0x1 <<  7) /* (EMAC) */#define AT91C_EMAC_TIDLE	((unsigned int) 0x1 <<  8) /* (EMAC) */#define AT91C_EMAC_LINK		((unsigned int) 0x1 <<  9) /* (EMAC) */#define AT91C_EMAC_ROVR		((unsigned int) 0x1 << 10) /* (EMAC) */#define AT91C_EMAC_HRESP	((unsigned int) 0x1 << 11) /* (EMAC) *//* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- *//* -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- *//* -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- *//* -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- */#define AT91C_EMAC_DATA		((unsigned int) 0xFFFF <<  0) /* (EMAC) */#define AT91C_EMAC_CODE		((unsigned int) 0x3  << 16) /* (EMAC) */#define AT91C_EMAC_CODE_802_3	((unsigned int) 0x2  << 16) /* (EMAC) Write Operation */#define AT91C_EMAC_REGA		((unsigned int) 0x1F << 18) /* (EMAC) */#define AT91C_EMAC_PHYA		((unsigned int) 0x1F << 23) /* (EMAC) */#define AT91C_EMAC_RW		((unsigned int) 0x3  << 28) /* (EMAC) */#define AT91C_EMAC_RW_R		((unsigned int) 0x2  << 28) /* (EMAC) Read Operation */#define AT91C_EMAC_RW_W		((unsigned int) 0x1  << 28) /* (EMAC) Write Operation */#define AT91C_EMAC_HIGH		((unsigned int) 0x1  << 30) /* (EMAC) */#define AT91C_EMAC_LOW		((unsigned int) 0x1  << 31) /* (EMAC) *//******************************************************************************//*           SOFTWARE API DEFINITION  FOR Serial Parallel Interface           *//******************************************************************************/typedef struct _AT91S_SPI{	AT91_REG	 SPI_CR; 	/* Control Register */	AT91_REG	 SPI_MR; 	/* Mode Register */	AT91_REG	 SPI_RDR; 	/* Receive Data Register */	AT91_REG	 SPI_TDR; 	/* Transmit Data Register */	AT91_REG	 SPI_SR; 	/* Status Register */	AT91_REG	 SPI_IER; 	/* Interrupt Enable Register */	AT91_REG	 SPI_IDR; 	/* Interrupt Disable Register */	AT91_REG	 SPI_IMR; 	/* Interrupt Mask Register */	AT91_REG	 Reserved0[4]; 	/* */	AT91_REG	 SPI_CSR[4]; 	/* Chip Select Register */	AT91_REG	 Reserved1[48]; /* */	AT91_REG	 SPI_RPR; 	/* Receive Pointer Register */	AT91_REG	 SPI_RCR; 	/* Receive Counter Register */	AT91_REG	 SPI_TPR; 	/* Transmit Pointer Register */	AT91_REG	 SPI_TCR; 	/* Transmit Counter Register */	AT91_REG	 SPI_RNPR; 	/* Receive Next Pointer Register */	AT91_REG	 SPI_RNCR; 	/* Receive Next Counter Register */	AT91_REG	 SPI_TNPR; 	/* Transmit Next Pointer Register */	AT91_REG	 SPI_TNCR; 	/* Transmit Next Counter Register */	AT91_REG	 SPI_PTCR; 	/* PDC Transfer Control Register */	AT91_REG	 SPI_PTSR; 	/* PDC Transfer Status Register */} AT91S_SPI, *AT91PS_SPI;/* -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- */#define AT91C_SPI_SPIEN		((unsigned int) 0x1 <<  0) /* (SPI) SPI Enable */#define AT91C_SPI_SPIDIS	((unsigned int) 0x1 <<  1) /* (SPI) SPI Disable */#define AT91C_SPI_SWRST		((unsigned int) 0x1 <<  7) /* (SPI) SPI Software reset *//* -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- */#define AT91C_SPI_MSTR		((unsigned int) 0x1 <<  0) /* (SPI) Master/Slave Mode */#define AT91C_SPI_PS		((unsigned int) 0x1 <<  1) /* (SPI) Peripheral Select */#define AT91C_SPI_PS_FIXED	((unsigned int) 0x0 <<  1) /* (SPI) Fixed Peripheral Select */#define AT91C_SPI_PS_VARIABLE	((unsigned int) 0x1 <<  1) /* (SPI) Variable Peripheral Select */#define AT91C_SPI_PCSDEC	((unsigned int) 0x1 <<  2) /* (SPI) Chip Select Decode */#define AT91C_SPI_DIV32		((unsigned int) 0x1 <<  3) /* (SPI) Clock Selection */#define AT91C_SPI_MODFDIS	((unsigned int) 0x1 <<  4) /* (SPI) Mode Fault Detection */#define AT91C_SPI_LLB		((unsigned int) 0x1 <<  7) /* (SPI) Clock Selection */#define AT91C_SPI_PCS		((unsigned int) 0xF << 16) /* (SPI) Peripheral Chip Select */#define AT91C_SPI_DLYBCS	((unsigned int) 0xFF << 24) /* (SPI) Delay Between Chip Selects *//* -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- */#define AT91C_SPI_RD		((unsigned int) 0xFFFF <<  0) /* (SPI) Receive Data */#define AT91C_SPI_RPCS		((unsigned int) 0xF << 16) /* (SPI) Peripheral Chip Select Status *//* -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- */#define AT91C_SPI_TD		((unsigned int) 0xFFFF <<  0) /* (SPI) Transmit Data */#define AT91C_SPI_TPCS		((unsigned int) 0xF << 16) /* (SPI) Peripheral Chip Select Status *//* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */#define AT91C_SPI_RDRF		((unsigned int) 0x1 <<  0) /* (SPI) Receive Data Register Full */#define AT91C_SPI_TDRE		((unsigned int) 0x1 <<  1) /* (SPI) Transmit Data Register Empty */#define AT91C_SPI_MODF		((unsigned int) 0x1 <<  2) /* (SPI) Mode Fault Error */#define AT91C_SPI_OVRES		((unsigned int) 0x1 <<  3) /* (SPI) Overrun Error Status */#define AT91C_SPI_SPENDRX	((unsigned int) 0x1 <<  4) /* (SPI) End of Receiver Transfer */#define AT91C_SPI_SPENDTX	((unsigned int) 0x1 <<  5) /* (SPI) End of Receiver Transfer */#define AT91C_SPI_RXBUFF	((unsigned int) 0x1 <<  6) /* (SPI) RXBUFF Interrupt */#define AT91C_SPI_TXBUFE	((unsigned int) 0x1 <<  7) /* (SPI) TXBUFE Interrupt */#define AT91C_SPI_SPIENS	((unsigned int) 0x1 << 16) /* (SPI) Enable Status *//* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- *//* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- *//* -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- *//* -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- */#define AT91C_SPI_CPOL		((unsigned int) 0x1  <<  0) /* (SPI) Clock Polarity */#define AT91C_SPI_NCPHA		((unsigned int) 0x1  <<  1) /* (SPI) Clock Phase */#define AT91C_SPI_BITS		((unsigned int) 0xF  <<  4) /* (SPI) Bits Per Transfer */#define AT91C_SPI_BITS_8	((unsigned int) 0x0  <<  4) /* (SPI) 8 Bits Per transfer */#define AT91C_SPI_BITS_9	((unsigned int) 0x1  <<  4) /* (SPI) 9 Bits Per transfer */#define AT91C_SPI_BITS_10	((unsigned int) 0x2  <<  4) /* (SPI) 10 Bits Per transfer */#define AT91C_SPI_BITS_11	((unsigned int) 0x3  <<  4) /* (SPI) 11 Bits Per transfer */#define AT91C_SPI_BITS_12	((unsigned int) 0x4  <<  4) /* (SPI) 12 Bits Per transfer */#define AT91C_SPI_BITS_13	((unsigned int) 0x5  <<  4) /* (SPI) 13 Bits Per transfer */#define AT91C_SPI_BITS_14	((unsigned int) 0x6  <<  4) /* (SPI) 14 Bits Per transfer */#define AT91C_SPI_BITS_15	((unsigned int) 0x7  <<  4) /* (SPI) 15 Bits Per transfer */#define AT91C_SPI_BITS_16	((unsigned int) 0x8  <<  4) /* (SPI) 16 Bits Per transfer */#define AT91C_SPI_SCBR		((unsigned int) 0xFF <<  8) /* (SPI) Serial Clock Baud Rate */#define AT91C_SPI_DLYBS		((unsigned int) 0xFF << 16) /* (SPI) Serial Clock Baud Rate */#define AT91C_SPI_DLYBCT	((unsigned int) 0xFF << 24) /* (SPI) Delay Between Consecutive Transfers *//******************************************************************************//*           SOFTWARE API DEFINITION  FOR Peripheral Data Controller          *//******************************************************************************/typedef struct _AT91S_PDC{	AT91_REG	 PDC_RPR; 	/* Receive Pointer Register */	AT91_REG	 PDC_RCR; 	/* Receive Counter Register */	AT91_REG	 PDC_TPR; 	/* Transmit Pointer Register */	AT91_REG	 PDC_TCR; 	/* Transmit Counter Register */	AT91_REG	 PDC_RNPR; 	/* Receive Next Pointer Register */	AT91_REG	 PDC_RNCR; 	/* Receive Next Counter Register */	AT91_REG	 PDC_TNPR; 	/* Transmit Next Pointer Register */	AT91_REG	 PDC_TNCR; 	/* Transmit Next Counter Register */	AT91_REG	 PDC_PTCR; 	/* PDC Transfer Control Register */	AT91_REG	 PDC_PTSR; 	/* PDC Transfer Status Register */} AT91S_PDC, *AT91PS_PDC;