?? atm.c
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/*-----------------------------------------------------------------*/ /* SRFCR - SAR receive function code */ /* 0-2 rsvd = 000 */ /* 3-4 BO = 11 Byte ordering (big endian). */ /* 5-7 FC = 000 Value driven on the address type signals AT[1-3] */ /* when the SDMA channel accesses memory. */ /*-----------------------------------------------------------------*/ *SRFCR(immr) = 0x18; /*-----------------------------------------------------------------*/ /* SRSTATE - SAR receive status */ /* 0 EXT = 0 Extended mode off. */ /* 1 ACP = 0 Valid only if EXT = 1. */ /* 2 EC = 0 Standard 53-byte ATM cell. */ /* 3 SNC = 0 In sync. Must be set to 0 during initialization. */ /* 4 ESAR = 1 Enhanced SAR functionality enabled. */ /* 5 MCF = 1 Management Cell Filter active. */ /* 6 SER = 0 UTOPIA mode. */ /* 7 MPY = 1 Multiple PHY mode. */ /*-----------------------------------------------------------------*/ *SRSTATE(immr) = 0x0D; /*-----------------------------------------------------------------*/ /* MRBLR - Maximum receive buffer length register. */ /* Must be cleared for ATM operation (see also SMRBLR). */ /*-----------------------------------------------------------------*/ *MRBLR(immr) = 0; /*-----------------------------------------------------------------*/ /* RSTATE - SCC internal receive state parameters */ /* The first byte must be initialized with the value of SRFCR. */ /*-----------------------------------------------------------------*/ *RSTATE(immr) = (uint32)(*SRFCR(immr)) << 24; /*-----------------------------------------------------------------*/ /* STFCR - SAR transmit function code */ /* 0-2 rsvd = 000 */ /* 3-4 BO = 11 Byte ordering (big endian). */ /* 5-7 FC = 000 Value driven on the address type signals AT[1-3] */ /* when the SDMA channel accesses memory. */ /*-----------------------------------------------------------------*/ *STFCR(immr) = 0x18; /*-----------------------------------------------------------------*/ /* SRSTATE - SAR transmit status */ /* 0 EXT = 0 : Extended mode off */ /* 1 rsvd = 0 : */ /* 2 EC = 0 : Standard 53-byte ATM cell */ /* 3 rsvd = 0 : */ /* 4 ESAR = 1 : Enhanced SAR functionality enabled */ /* 5 rsvd = 0 : */ /* 6 SER = 0 : UTOPIA mode */ /* 7 MPY = 1 : Multiple PHY mode */ /*-----------------------------------------------------------------*/ *STSTATE(immr) = 0x09; /*-----------------------------------------------------------------*/ /* TBDBASE - Transmit buffer descriptors base address */ /* The TBDs reside in cache safe external memory. */ /*-----------------------------------------------------------------*/ *TBDBASE(immr) = (uint32)g_atm.tbd_base_ptr; /*-----------------------------------------------------------------*/ /* TSTATE - SCC internal transmit state parameters */ /* The first byte must be initialized with the value of STFCR. */ /*-----------------------------------------------------------------*/ *TSTATE(immr) = (uint32)(*STFCR(immr)) << 24; /*-----------------------------------------------------------------*/ /* CTBASE - Connection table base address */ /* Offset from the beginning of DPRAM (64-byte aligned). */ /*-----------------------------------------------------------------*/ *CTBASE(immr) = CT_BASE; /*-----------------------------------------------------------------*/ /* INTBASE - Interrupt queue base pointer. */ /* The interrupt queue resides in cache safe external memory. */ /*-----------------------------------------------------------------*/ *INTBASE(immr) = (uint32)g_atm.int_reload_ptr; /*-----------------------------------------------------------------*/ /* INTPTR - Pointer into interrupt queue. */ /* Initialize to INTBASE. */ /*-----------------------------------------------------------------*/ *INTPTR(immr) = *INTBASE(immr); /*-----------------------------------------------------------------*/ /* C_MASK - Constant mask for CRC32 */ /* Must be initialized to 0xDEBB20E3. */ /*-----------------------------------------------------------------*/ *C_MASK(immr) = 0xDEBB20E3; /*-----------------------------------------------------------------*/ /* INT_ICNT - Interrupt threshold value */ /*-----------------------------------------------------------------*/ *INT_ICNT(immr) = 1; /*-----------------------------------------------------------------*/ /* INT_CNT - Interrupt counter */ /* Initalize to INT_ICNT. Decremented for each interrupt entry */ /* reported in the interrupt queue. On zero an interrupt is */ /* signaled to the host by setting the GINT bit in the event */ /* register. The counter is reinitialized with INT_ICNT. */ /*-----------------------------------------------------------------*/ *INT_CNT(immr) = *INT_ICNT(immr); /*-----------------------------------------------------------------*/ /* SMRBLR - SAR maximum receive buffer length register. */ /* Must be a multiple of 48 bytes. Common for all ATM connections. */ /*-----------------------------------------------------------------*/ *SMRBLR(immr) = SAR_RXB_SIZE; /*-----------------------------------------------------------------*/ /* APCST - APC status register. */ /* 0 rsvd 0 */ /* 1-2 CSER 11 Initialize with the same value as NSER. */ /* 3-4 NSER 11 Next serial or UTOPIA channel. */ /* 5-7 rsvd 000 */ /* 8-10 rsvd 000 */ /* 11 rsvd 0 */ /* 12 ESAR 1 UTOPIA Level 2 MPHY enabled. */ /* 13 DIS 0 APC disable. Must be initiazed to 0. */ /* 14 PL2 0 Not used. */ /* 15 MPY 1 Multiple PHY mode on. */ /*-----------------------------------------------------------------*/ *APCST(immr) = 0x7809; /*-----------------------------------------------------------------*/ /* APCPTR - Pointer to the APC parameter table */ /* In MPHY master mode this parameter points to the MPHY pointing */ /* table. 2-byte aligned. */ /*-----------------------------------------------------------------*/ *APCPTR(immr) = MPHYPT_BASE; /*-----------------------------------------------------------------*/ /* HMASK - Header mask */ /* Each incoming cell is masked with HMASK before being compared */ /* to the entries in the address matching table. */ /*-----------------------------------------------------------------*/ *HMASK(immr) = AM_HMASK; /*-----------------------------------------------------------------*/ /* AMBASE - Address matching table base address */ /*-----------------------------------------------------------------*/ *AMBASE(immr) = AM_BASE; /*-----------------------------------------------------------------*/ /* AMEND - Address matching table end address */ /*-----------------------------------------------------------------*/ *AMEND(immr) = AM_BASE; /*-----------------------------------------------------------------*/ /* APBASE - Address pointing table base address */ /*-----------------------------------------------------------------*/ *APBASE(immr) = AP_BASE; /*-----------------------------------------------------------------*/ /* MPHYST - MPHY status register */ /* 0-1 rsvd 00 */ /* 2-6 NMPHY 00000 1 PHY */ /* 7-9 rsvd 000 */ /* 10-14 CMPHY 00000 Initialize with same value as NMPHY */ /*-----------------------------------------------------------------*/ *MPHYST(immr) = 0x0000; /*-----------------------------------------------------------------*/ /* TCTEBASE - Transmit connection table extension base address */ /* Offset from the beginning of DPRAM (32-byte aligned). */ /*-----------------------------------------------------------------*/ *TCTEBASE(immr) = TCTE_BASE; /*-----------------------------------------------------------------*/ /* Clear not used registers. */ /*-----------------------------------------------------------------*/}/***************************************************************************** * * FUNCTION NAME: atmUtpInit * * DESCRIPTION: * * This function initializes the ATM interface for * * - UTOPIA mode * - muxed bus * - master operation * - multi PHY (because of a bug in the MPC860P rev. E.0) * - internal clock = SYSCLK / 2 * * EXTERNAL EFFECTS: * * After calling this function, the MPC860ESAR UTOPIA bus is * active and uses the following ports/pins: * * Port Pin Signal Description * ------ --- ------- ------------------------------------------- * PB[15] R17 TxClav Transmit cell available input/output signal * PC[15] D16 RxClav Receive cell available input/output signal * PD[15] U17 UTPB[0] UTOPIA bus bit 0 input/output signal * PD[14] V19 UTPB[1] UTOPIA bus bit 1 input/output signal * PD[13] V18 UTPB[2] UTOPIA bus bit 2 input/output signal * PD[12] R16 UTPB[3] UTOPIA bus bit 3 input/output signal * PD[11] T16 RXENB Receive enable input/output signal * PD[10] W18 TXENB Transmit enable input/output signal * PD[9] V17 UTPCLK UTOPIA clock input/output signal * PD[7] T15 UTPB[4] UTOPIA bus bit 4 input/output signal * PD[6] V16 UTPB[5] UTOPIA bus bit 5 input/output signal * PD[5] U15 UTPB[6] UTOPIA bus bit 6 input/output signal * PD[4] U16 UTPB[7] UTOPIA bus bit 7 input/output signal * PD[3] W16 SOC Start of cell input/output signal * * PARAMETERS: none * * RETURNS: void * * REMARK: * * The ATM parameters and data structures must be configured before * initializing the UTOPIA port. The UTOPIA port activates immediately * upon initialization, and if its associated data structures are not * initialized, the CPM will lock up. * ****************************************************************************/void atmUtpInit(){ volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile iop8xx_t *iop = &immap->im_ioport; volatile car8xx_t *car = &immap->im_clkrst; volatile cpm8xx_t *cpm = &immap->im_cpm; int flag; flag = disable_interrupts(); /*-----------------------------------------------------------------*/ /* SCCR - System Clock Control Register */ /* */ /* The UTOPIA clock can be selected to be internal clock or */ /* external clock (selected by the UTOPIA mode register). */ /* In case of internal clock, the UTOPIA clock is derived from */ /* the system frequency divided by two dividers. */ /* Bits 27-31 of the SCCR register are defined to control the */ /* UTOPIA clock. */ /* */ /* SCCR[27:29] DFUTP Division factor. Divide the system clock */ /* by 2^DFUTP. */ /* SCCR[30:31] DFAUTP Additional division factor. Divide the */ /* system clock by the following value: */ /* 00 = divide by 1 */ /* 00 = divide by 3 */ /* 10 = divide by 5 */ /* 11 = divide by 7 */ /* */ /* Note that the UTOPIA clock must be programmed as to operate */ /* within the range SYSCLK/10 .. 50Mhz. */ /*-----------------------------------------------------------------*/ car->car_sccr &= 0xFFFFFFE0; car->car_sccr |= 0x00000008; /* UTPCLK = SYSCLK / 4 */ /*-----------------------------------------------------------------*/ /* RCCR - RISC Controller Configuration Register */ /* */ /* RCCR[8] DR1M IDMA Request 0 Mode */ /* 0 = edge sensitive */ /* 1 = level sensitive */ /* RCCR[9] DR0M IDMA Request 0 Mode */ /* 0 = edge sensitive */ /* 1 = level sensitive */ /* RCCR[10:11] DRQP IDMA Request Priority */ /* 00 = IDMA req. have more prio. than SCCs */ /* 01 = IDMA req. have less prio. then SCCs */ /* 10 = IDMA requests have the lowest prio. */ /* 11 = reserved */ /* */ /* The RCCR[DR0M] and RCCR[DR1M] bits must be set to enable UTOPIA */ /* operation. Also, program RCCR[DPQP] to 01 to give SCC transfers */ /* higher priority. */ /*-----------------------------------------------------------------*/ cpm->cp_rccr &= 0xFF0F; cpm->cp_rccr |= 0x00D0; /*-----------------------------------------------------------------*/ /* Port B - TxClav Signal */ /*-----------------------------------------------------------------*/ cpm->cp_pbpar |= 0x00010000; /* PBPAR[15] = 1 */ cpm->cp_pbdir &= 0xFFFEFFFF; /* PBDIR[15] = 0 */ /*-----------------------------------------------------------------*/ /* UTOPIA Mode Register */ /* */ /* - muxed bus (master operation only) */ /* - multi PHY (because of a bug in the MPC860P rev.E.0) */ /* - internal clock */ /* - no loopback */ /* - do no activate statistical counters */ /*-----------------------------------------------------------------*/ iop->utmode = 0x00000004; SYNC; /*-----------------------------------------------------------------*/ /* Port D - UTOPIA Data and Control Signals */ /* */ /* 15-12 UTPB[0:3] UTOPIA bus bit 0 - 3 input/output signals */ /* 11 RXENB UTOPIA receive enable input/output signal */ /* 10 TXENB UTOPIA transmit enable input/output signal */ /* 9 TUPCLK UTOPIA clock input/output signal */ /* 8 MII-MDC Used by MII in simult. MII and UTOPIA operation */ /* 7-4 UTPB[4:7] UTOPIA bus bit 4 - 7 input/output signals */ /* 3 SOC UTOPIA Start of cell input/output signal */ /* 2 Reserved */ /* 1 Enable UTOPIA mode */ /* 0 Enable SAR */ /*-----------------------------------------------------------------*/ iop->iop_pdpar |= 0xDF7F; SYNC; iop->iop_pddir &= 0x2080; SYNC; /*-----------------------------------------------------------------*/ /* Port C - RxClav Signal */ /*-----------------------------------------------------------------*/ iop->iop_pcpar |= 0x0001; /* PCPAR[15] = 1 */ iop->iop_pcdir &= 0xFFFE; /* PCDIR[15] = 0 */ iop->iop_pcso &= 0xFFFE; /* PCSO[15] = 0 */ if (flag) enable_interrupts();}?? 快捷鍵說明
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