** This function gets the device interrupt pending register contents.* This register indicates the pending interrupt sources, those that are waiting* to be serviced by the software, for a device which contains the IPIF.* An interrupt must be enabled in the interrupt enable register of the IPIF to* be pending.** Each bit of the register correlates to a specific interrupt source within the* the device which contains the IPIF.  With the exception of some internal IPIF* conditions, the contents of this register are not latched since the condition* is latched in the IP interrupt status register, by an internal block of the* IPIF such as a FIFO or DMA channel, or by the IP of the device.  This register* is read only and is not latched, but it is necessary to acknowledge (clear)* the interrupt condition by performing the appropriate processing for the IP* or block within the IPIF.** This register can be thought of as the contents of the interrupt status* register ANDed with the contents of the interrupt enable register.** ARGUMENTS:** RegBaseAddress contains the base address of the IPIF registers.** RETURN VALUE:** The value read from the interrupt pending register of the device.  The bit* definitions are specific to the device with the exception of the latched* internal IPIF condition bits. The following values may be used to detect* internal IPIF conditions in the value.**   XIIF_V123B_ERROR_MASK     Indicates a device error in the IPIF** NOTES:** None.*******************************************************************************/#define XIIF_V123B_READ_DIPR(RegBaseAddress) \    XIo_In32((RegBaseAddress) + XIIF_V123B_DIPR_OFFSET)/******************************************************************************** MACRO:** XIIF_V123B_READ_DIIR** DESCRIPTION:** This function gets the device interrupt ID for the highest priority interrupt* which is pending from the interrupt ID register. This function provides* priority resolution such that faster interrupt processing is possible.* Without priority resolution, it is necessary for the software to read the* interrupt pending register and then check each interrupt source to determine* if an interrupt is pending.  Priority resolution becomes more important as the* number of interrupt sources becomes larger.** Interrupt priorities are based upon the bit position of the interrupt in the* interrupt pending register with bit 0 being the highest priority. The* interrupt ID is the priority of the interrupt, 0 - 31, with 0 being the* highest priority. The interrupt ID register is live rather than latched such* that multiple calls to this function may not yield the same results.	A* special value, outside of the interrupt priority range of 0 - 31, is* contained in the register which indicates that no interrupt is pending.  This* may be useful for allowing software to continue processing interrupts in a* loop until there are no longer any interrupts pending.** The interrupt ID is designed to allow a function pointer table to be used* in the software such that the interrupt ID is used as an index into that* table.  The function pointer table could contain an instance pointer, such* as to DMA channel, and a function pointer to the function which handles* that interrupt.  This design requires the interrupt processing of the device* driver to be partitioned into smaller more granular pieces based upon* hardware used by the device, such as DMA channels and FIFOs.** It is not mandatory that this function be used by the device driver software.* It may choose to read the pending register and resolve the pending interrupt* priorities on it's own.** ARGUMENTS:** RegBaseAddress contains the base address of the IPIF registers.** RETURN VALUE:** An interrupt ID, 0 - 31, which identifies the highest priority interrupt* which is pending.  A value of XIIF_NO_INTERRUPT_ID indicates that there is* no interrupt pending. The following values may be used to identify the* interrupt ID for the internal IPIF interrupts.**   XIIF_V123B_ERROR_INTERRUPT_ID     Indicates a device error in the IPIF** NOTES:** None.*******************************************************************************/#define XIIF_V123B_READ_DIIR(RegBaseAddress) \    XIo_In32((RegBaseAddress) + XIIF_V123B_DIIR_OFFSET)/******************************************************************************** MACRO:** XIIF_V123B_GLOBAL_INTR_DISABLE** DESCRIPTION:** This function disables all interrupts for the device by writing to the global* interrupt enable register.  This register provides the ability to disable* interrupts without any modifications to the interrupt enable register such* that it is minimal effort to restore the interrupts to the previous enabled* state.  The corresponding function, XIpIf_GlobalIntrEnable, is provided to* restore the interrupts to the previous enabled state.	 This function is* designed to be used in critical sections of device drivers such that it is* not necessary to disable other device interrupts.** ARGUMENTS:** RegBaseAddress contains the base address of the IPIF registers.** RETURN VALUE:** None.** NOTES:** None.*******************************************************************************/#define XIIF_V123B_GINTR_DISABLE(RegBaseAddress) \    XIo_Out32((RegBaseAddress) + XIIF_V123B_DGIER_OFFSET, 0)/******************************************************************************** MACRO:** XIIF_V123B_GINTR_ENABLE** DESCRIPTION:** This function writes to the global interrupt enable register to enable* interrupts from the device.  This register provides the ability to enable* interrupts without any modifications to the interrupt enable register such* that it is minimal effort to restore the interrupts to the previous enabled* state.  This function does not enable individual interrupts as the interrupt* enable register must be set appropriately.  This function is designed to be* used in critical sections of device drivers such that it is not necessary to* disable other device interrupts.** ARGUMENTS:** RegBaseAddress contains the base address of the IPIF registers.** RETURN VALUE:** None.** NOTES:** None.*******************************************************************************/#define XIIF_V123B_GINTR_ENABLE(RegBaseAddress)		  \    XIo_Out32((RegBaseAddress) + XIIF_V123B_DGIER_OFFSET, \	       XIIF_V123B_GINTR_ENABLE_MASK)/******************************************************************************** MACRO:** XIIF_V123B_IS_GINTR_ENABLED** DESCRIPTION:** This function determines if interrupts are enabled at the global level by* reading the gloabl interrupt register. This register provides the ability to* disable interrupts without any modifications to the interrupt enable register* such that it is minimal effort to restore the interrupts to the previous* enabled state.** ARGUMENTS:** RegBaseAddress contains the base address of the IPIF registers.** RETURN VALUE:** XTRUE if interrupts are enabled for the IPIF, XFALSE otherwise.** NOTES:** None.*******************************************************************************/#define XIIF_V123B_IS_GINTR_ENABLED(RegBaseAddress)		\    (XIo_In32((RegBaseAddress) + XIIF_V123B_DGIER_OFFSET) ==	\	      XIIF_V123B_GINTR_ENABLE_MASK)/******************************************************************************** MACRO:** XIIF_V123B_WRITE_IISR** DESCRIPTION:** This function sets the IP interrupt status register to the specified value.* This register indicates the status of interrupt sources for the IP of the* device.  The IP is defined as the part of the device that connects to the* IPIF.	 The status is independent of whether interrupts are enabled such that* the status register may also be polled when interrupts are not enabled.** Each bit of the register correlates to a specific interrupt source within the* IP.  All bits of this register are latched. Setting a bit which is zero* within this register causes an interrupt to be generated.  The device global* interrupt enable register and the device interrupt enable register must be set* appropriately to allow an interrupt to be passed out of the device. The* interrupt is cleared by writing to this register with the bits to be* cleared set to a one and all others to zero.	This register implements a* toggle on write functionality meaning any bits which are set in the value* written cause the bits in the register to change to the opposite state.** This function writes only the specified value to the register such that* some status bits may be set and others cleared.  It is the caller's* responsibility to get the value of the register prior to setting the value* to prevent an destructive behavior.** ARGUMENTS:** RegBaseAddress contains the base address of the IPIF registers.** Status contains the value to be written to the IP interrupt status* register.  The bit definitions are specific to the device IP.** RETURN VALUE:** None.** NOTES:** None.*******************************************************************************/#define XIIF_V123B_WRITE_IISR(RegBaseAddress, Status) \    XIo_Out32((RegBaseAddress) + XIIF_V123B_IISR_OFFSET, (Status))/******************************************************************************** MACRO:** XIIF_V123B_READ_IISR** DESCRIPTION:** This function gets the contents of the IP interrupt status register.* This register indicates the status of interrupt sources for the IP of the* device.  The IP is defined as the part of the device that connects to the* IPIF. The status is independent of whether interrupts are enabled such* that the status register may also be polled when interrupts are not enabled.** Each bit of the register correlates to a specific interrupt source within the* device.  All bits of this register are latched.  Writing a 1 to a bit within* this register causes an interrupt to be generated if enabled in the interrupt* enable register and the global interrupt enable is set.  Since the status is* latched, each status bit must be acknowledged in order for the bit in the* status register to be updated.  Each bit can be acknowledged by writing a* 0 to the bit in the status register.* ARGUMENTS:** RegBaseAddress contains the base address of the IPIF registers.** RETURN VALUE:** A status which contains the value read from the IP interrupt status register.* The bit definitions are specific to the device IP.** NOTES:** None.*******************************************************************************/#define XIIF_V123B_READ_IISR(RegBaseAddress) \    XIo_In32((RegBaseAddress) + XIIF_V123B_IISR_OFFSET)/******************************************************************************** MACRO:** XIIF_V123B_WRITE_IIER** DESCRIPTION:** This function sets the IP interrupt enable register contents.	 This register* controls which interrupt sources of the IP are allowed to generate an* interrupt.  The global interrupt enable register and the device interrupt* enable register must also be set appropriately for an interrupt to be* passed out of the device containing the IPIF and the IP.** Each bit of the register correlates to a specific interrupt source within the* IP.  Setting a bit in this register enables the interrupt source to generate* an interrupt.	 Clearing a bit in this register disables interrupt generation* for that interrupt source.** This function writes only the specified value to the register such that* some interrupt sources may be enabled and others disabled.  It is the* caller's responsibility to get the value of the interrupt enable register* prior to setting the value to prevent an destructive behavior.** ARGUMENTS:** RegBaseAddress contains the base address of the IPIF registers.** Enable contains the value to be written to the IP interrupt enable register.* The bit definitions are specific to the device IP.** RETURN VALUE:** None.** NOTES:** None.*******************************************************************************/#define XIIF_V123B_WRITE_IIER(RegBaseAddress, Enable) \    XIo_Out32((RegBaseAddress) + XIIF_V123B_IIER_OFFSET, (Enable))/******************************************************************************** MACRO:** XIIF_V123B_READ_IIER** DESCRIPTION:*** This function gets the IP interrupt enable register contents.	 This register* controls which interrupt sources of the IP are allowed to generate an* interrupt.  The global interrupt enable register and the device interrupt* enable register must also be set appropriately for an interrupt to be* passed out of the device containing the IPIF and the IP.** Each bit of the register correlates to a specific interrupt source within the* IP.  Setting a bit in this register enables the interrupt source to generate* an interrupt.	 Clearing a bit in this register disables interrupt generation* for that interrupt source.** ARGUMENTS:** RegBaseAddress contains the base address of the IPIF registers.** RETURN VALUE:** The contents read from the IP interrupt enable register.  The bit definitions* are specific to the device IP.** NOTES:** Signature: u32 XIIF_V123B_READ_IIER(u32 RegBaseAddress)*******************************************************************************/#define XIIF_V123B_READ_IIER(RegBaseAddress) \    XIo_In32((RegBaseAddress) + XIIF_V123B_IIER_OFFSET)/************************** Function Prototypes ******************************//* * Initialization Functions */XStatus XIpIfV123b_SelfTest(u32 RegBaseAddress, u8 IpRegistersWidth);#endif				/* end of protection macro */