* occurs when the no ack is done to tell the slave the last byte		 */		if (ByteCount == 1) {			IntrStatusMask =				XIIC_INTR_ARB_LOST_MASK | XIIC_INTR_BNB_MASK;		} else {			IntrStatusMask =				XIIC_INTR_ARB_LOST_MASK |				XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_BNB_MASK;		}		/* Wait for the previous transmit and the 1st receive to complete		 * by checking the interrupt status register of the IPIF		 */		while (1) {			IntrStatus = XIIF_V123B_READ_IISR (BaseAddress);			if (IntrStatus & XIIC_INTR_RX_FULL_MASK) {				break;			}			/* Check the transmit error after the receive full because when			 * sending only one byte transmit error will occur because of the			 * no ack to indicate the end of the data			 */			if (IntrStatus & IntrStatusMask) {				return ByteCount;			}		}		CntlReg = XIo_In8 (BaseAddress + XIIC_CR_REG_OFFSET);		/* Special conditions exist for the last two bytes so check for them		 * Note that the control register must be setup for these conditions		 * before the data byte which was already received is read from the		 * receive FIFO (while the bus is throttled		 */		if (ByteCount == 1) {			/* For the last data byte, it has already been read and no ack			 * has been done, so clear MSMS while leaving the device enabled			 * so it can get off the IIC bus appropriately with a stop.			 */			XIo_Out8 (BaseAddress + XIIC_CR_REG_OFFSET,				  XIIC_CR_ENABLE_DEVICE_MASK);		}		/* Before the last byte is received, set NOACK to tell the slave IIC		 * device that it is the end, this must be done before reading the byte		 * from the FIFO		 */		if (ByteCount == 2) {			/* Write control reg with NO ACK allowing last byte to			 * have the No ack set to indicate to slave last byte read.			 */			XIo_Out8 (BaseAddress + XIIC_CR_REG_OFFSET,				  CntlReg | XIIC_CR_NO_ACK_MASK);		}		/* Read in data from the FIFO and unthrottle the bus such that the		 * next byte is read from the IIC bus		 */		*BufferPtr++ = XIo_In8 (BaseAddress + XIIC_DRR_REG_OFFSET);		/* Clear the latched interrupt status so that it will be updated with		 * the new state when it changes, this must be done after the receive		 * register is read		 */		XIic_mClearIisr (BaseAddress, XIIC_INTR_RX_FULL_MASK |				 XIIC_INTR_TX_ERROR_MASK |				 XIIC_INTR_ARB_LOST_MASK);		ByteCount--;	}	/* Wait for the bus to transition to not busy before returning, the IIC	 * device cannot be disabled until this occurs.	 It should transition as	 * the MSMS bit of the control register was cleared before the last byte	 * was read from the FIFO.	 */	while (1) {		if (XIIF_V123B_READ_IISR (BaseAddress) & XIIC_INTR_BNB_MASK) {			break;		}	}	return ByteCount;}/****************************************************************************//*** Send data as a master on the IIC bus.	 This function sends the data* using polled I/O and blocks until the data has been sent.  It only supports* 7 bit addressing and non-repeated start modes of operation.  The user is* responsible for ensuring the bus is not busy if multiple masters are present* on the bus.** @param    BaseAddress contains the base address of the IIC device.* @param    Address contains the 7 bit IIC address of the device to send the*	    specified data to.* @param    BufferPtr points to the data to be sent.* @param    ByteCount is the number of bytes to be sent.** @return** The number of bytes sent.** @note** None*******************************************************************************/unsigned XIic_Send (u32 BaseAddress, u8 Address,		    u8 * BufferPtr, unsigned ByteCount){	unsigned RemainingByteCount;	/* Put the address into the FIFO to be sent and indicate that the operation	 * to be performed on the bus is a write operation	 */	XIic_mSend7BitAddress (BaseAddress, Address, XIIC_WRITE_OPERATION);	/* Clear the latched interrupt status so that it will be updated with the	 * new state when it changes, this must be done after the address is put	 * in the FIFO	 */	XIic_mClearIisr (BaseAddress, XIIC_INTR_TX_EMPTY_MASK |			 XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_ARB_LOST_MASK);	/* MSMS must be set after putting data into transmit FIFO, indicate the	 * direction is transmit, this device is master and enable the IIC device	 */	XIo_Out8 (BaseAddress + XIIC_CR_REG_OFFSET,		  XIIC_CR_MSMS_MASK | XIIC_CR_DIR_IS_TX_MASK |		  XIIC_CR_ENABLE_DEVICE_MASK);	/* Clear the latched interrupt	 * status for the bus not busy bit which must be done while the bus is busy	 */	XIic_mClearIisr (BaseAddress, XIIC_INTR_BNB_MASK);	/* Send the specified data to the device on the IIC bus specified by the	 * the address	 */	RemainingByteCount = SendData (BaseAddress, BufferPtr, ByteCount);	/*	 * The send is complete, disable the IIC device and return the number of	 * bytes that was sent	 */	XIo_Out8 (BaseAddress + XIIC_CR_REG_OFFSET, 0);	return ByteCount - RemainingByteCount;}/******************************************************************************** Send the specified buffer to the device that has been previously addressed* on the IIC bus.  This function assumes that the 7 bit address has been sent* and it should wait for the transmit of the address to complete.** @param    BaseAddress contains the base address of the IIC device.* @param    BufferPtr points to the data to be sent.* @param    ByteCount is the number of bytes to be sent.** @return** The number of bytes remaining to be sent.** @note** This function does not take advantage of the transmit FIFO because it is* designed for minimal code space and complexity.  It contains loops that* that could cause the function not to return if the hardware is not working.*******************************************************************************/static unsigned SendData (u32 BaseAddress, u8 * BufferPtr, unsigned ByteCount){	u32 IntrStatus;	/* Send the specified number of bytes in the specified buffer by polling	 * the device registers and blocking until complete	 */	while (ByteCount > 0) {		/* Wait for the transmit to be empty before sending any more data		 * by polling the interrupt status register		 */		while (1) {			IntrStatus = XIIF_V123B_READ_IISR (BaseAddress);			if (IntrStatus & (XIIC_INTR_TX_ERROR_MASK |					  XIIC_INTR_ARB_LOST_MASK |					  XIIC_INTR_BNB_MASK)) {				return ByteCount;			}			if (IntrStatus & XIIC_INTR_TX_EMPTY_MASK) {				break;			}		}		/* If there is more than one byte to send then put the next byte to send		 * into the transmit FIFO		 */		if (ByteCount > 1) {			XIo_Out8 (BaseAddress + XIIC_DTR_REG_OFFSET,				  *BufferPtr++);		} else {			/* Set the stop condition before sending the last byte of data so that			 * the stop condition will be generated immediately following the data			 * This is done by clearing the MSMS bit in the control register.			 */			XIo_Out8 (BaseAddress + XIIC_CR_REG_OFFSET,				  XIIC_CR_ENABLE_DEVICE_MASK |				  XIIC_CR_DIR_IS_TX_MASK);			/* Put the last byte to send in the transmit FIFO */			XIo_Out8 (BaseAddress + XIIC_DTR_REG_OFFSET,				  *BufferPtr++);		}		/* Clear the latched interrupt status register and this must be done after		 * the transmit FIFO has been written to or it won't clear		 */		XIic_mClearIisr (BaseAddress, XIIC_INTR_TX_EMPTY_MASK);		/* Update the byte count to reflect the byte sent and clear the latched		 * interrupt status so it will be updated for the new state		 */		ByteCount--;	}	/* Wait for the bus to transition to not busy before returning, the IIC	 * device cannot be disabled until this occurs.	 * Note that this is different from a receive operation because the stop	 * condition causes the bus to go not busy.	 */	while (1) {		if (XIIF_V123B_READ_IISR (BaseAddress) & XIIC_INTR_BNB_MASK) {			break;		}	}	return ByteCount;}