b       row11x4or12x4row13x4:    ori     r20, r20, 0x0a    b       row11x4or12x4row11x2:    ori     r20, r20, 0x0frow11x4or12x4:    /* get the size of bank 0-1 */    li      r3, 0x001f          /* get bank size from spd for bank0/1 */    bl      spdRead    rlwinm  r16, r3, 2, 24, 29  /* calculate size in MByte (128 MB max.) */    li      r3, 0x0005          /* get number of banks from spd for bank0/1 */    bl      spdRead    cmpi    0, 0, r3, 2         /* 2 banks ? */    bne     SDRAMnobank1    mr      r17, r16SDRAMnobank1:    li      r3, 0x000c          /* get refresh from spd for bank0/1 */    bl      spdRead    andi.   r3, r3, 0x007f      /* mask selfrefresh bit */    li      r4, 0x1800          /* refesh cycle 1536 clocks left shifted 2 */    cmpli   0, 0, r3, 0x0000    /* 15.6 us ? */    beq     writeRefresh    li      r4, 0x0c00          /* refesh cycle 768 clocks left shifted 2 */    cmpli   0, 0, r3, 0x0002    /* 7.8 us ? */    beq     writeRefresh    li      r4, 0x3000          /* refesh cycle 3072 clocks left shifted 2 */    cmpli   0, 0, r3, 0x0003    /* 31.3 us ? */    beq     writeRefresh    li      r4, 0x6000          /* refesh cycle 6144 clocks left shifted 2 */    cmpli   0, 0, r3, 0x0004    /* 62.5 us ? */    beq     writeRefresh    li      r4, 0    ori     r4, r4, 0xc000      /* refesh cycle 8224 clocks left shifted 2 */    cmpli   0, 0, r3, 0x0005    /* 125 us ? */    beq     writeRefresh    b       memConfErrwriteRefresh:    lis     r21, 0x0400         /* preset MCCR2 value */    or      r21, r21, r4    /* Overwrite MCCR1 */    lis     r3, MPC106_REG@h    ori     r3, r3, MPC106_MCCR1    stwbrx  r3, 0, r1    eieio    stwbrx  r20, 0, r2    /* Overwrite MCCR2 */    lis     r3, MPC106_REG@h    ori     r3, r3, MPC106_MCCR2    stwbrx  r3, 0, r1    eieio    stwbrx  r21, 0, r2    /* set the memory boundary registers for bank 0-3 */    li      r20, 0    lis     r23, 0x0303    lis     r24, 0x0303    subi    r21, r16, 1         /* calculate end address bank0 */    li      r22, 1    cmpi    0, 0, r17, 0        /* bank1 present ? */    beq     nobank1    andi.   r3, r16, 0x00ff     /* calculate start address of bank1 */    andi.   r4, r16, 0x0300    rlwinm  r3, r3, 8, 16, 23    or      r20, r20, r3    or      r23, r23, r4    add     r16, r16, r17       /* add to total memory size */    subi    r3, r16, 1          /* calculate end address of bank1 */    andi.   r4, r3, 0x0300    andi.   r3, r3, 0x00ff    rlwinm  r3, r3, 8, 16, 23    or      r21, r21, r3    or      r24, r24, r4    ori     r22, r22, 2         /* enable bank1 */    b       bankOknobank1:    ori     r23, r23, 0x0300    /* set bank1 start to unused area */    ori     r24, r24, 0x0300    /* set bank1 end to unused area */bankOk:    addi    r3, r29, (Mactivate-MessageBlock)    bl      Printf    mr      r3, r16    bl      OutDec    addi    r3, r29, (Mact0123e-MessageBlock)    bl      Printf/* * overwrite MSAR1, MEAR1, EMSAR1, and EMEAR1 */    addis   r3, r0, 0x8000      /* ADDR_80 */    ori     r3, r3, 0x0080      /* MSAR1 */    stwbrx  r3, 0, r1    eieio    stwbrx  r20, 0, r2    addis   r3, r0, 0x8000      /* ADDR_88 */    ori     r3, r3, 0x0088      /* EMSAR1 */    stwbrx  r3, 0, r1    eieio    stwbrx  r23, 0, r2    addis   r3, r0, 0x8000      /* ADDR_90 */    ori     r3, r3, 0x0090      /* MEAR1 */    stwbrx  r3, 0, r1    eieio    stwbrx  r21, 0, r2    addis   r3, r0, 0x8000      /* ADDR_98 */    ori     r3, r3, 0x0098      /* EMEAR1 */    stwbrx  r3, 0, r1    eieio    stwbrx  r24, 0, r2    addis   r3, r0, 0x8000      /* ADDR_A0 */    ori     r3, r3, 0x00a0      /* MBER */    stwbrx  r3, 0, r1    eieio    stwbrx  r22, 0, r2/* * delay to let SDRAM go through several initialization/refresh cycles */    lis     r3, 3    mtctr   r3memStartWait_1:    bdnz    memStartWait_1    eieio/* * set LEDs end */    li      r3, 0xf    lis     r30, CFG_USR_LED_BASE@h    stb     r3, 2(r30)    sync    mtlr    r13    blr                         /* EXIT board_asm_init ... *//*----------------------------------------------------------------------------*//* * print a message to COM1 in polling mode (r10=COM1 port, r3=(char*)string) */Printf:    lis     r10, CFG_NS16550_COM1@h /* COM1 base address*/    ori     r10, r10, CFG_NS16550_COM1@lWaitChr:    lbz     r0, 5(r10)          /* read link status */    eieio    andi.   r0, r0, 0x40        /* mask transmitter empty bit */    beq     cr0, WaitChr        /* wait till empty */    lbzx    r0, r0, r3          /* get char */    stb     r0, 0(r10)          /* write to transmit reg */    eieio    addi    r3, r3, 1           /* next char */    lbzx    r0, r0, r3          /* get char */    cmpwi   cr1, r0, 0          /* end of string ? */    bne     cr1, WaitChr    blr/* * print a char to COM1 in polling mode (r10=COM1 port, r3=char) */OutChr:    lis     r10, CFG_NS16550_COM1@h /* COM1 base address*/    ori     r10, r10, CFG_NS16550_COM1@lOutChr1:    lbz     r0, 5(r10)          /* read link status */    eieio    andi.   r0, r0, 0x40        /* mask transmitter empty bit */    beq     cr0, OutChr1        /* wait till empty */    stb     r3, 0(r10)          /* write to transmit reg */    eieio    blr/* * print 8/4/2 digits hex value to COM1 in polling mode (r10=COM1 port, r3=val) */OutHex2:    li      r9, 4               /* shift reg for 2 digits */    b       OHstartOutHex4:    li      r9, 12              /* shift reg for 4 digits */    b       OHstartOutHex:    li      r9, 28              /* shift reg for 8 digits */OHstart:    lis     r10, CFG_NS16550_COM1@h /* COM1 base address*/    ori     r10, r10, CFG_NS16550_COM1@lOutDig:    lbz     r0, 0(r29)          /* slow down dummy read */    lbz     r0, 5(r10)          /* read link status */    eieio    andi.   r0, r0, 0x40        /* mask transmitter empty bit */    beq     cr0, OutDig    sraw    r0, r3, r9    clrlwi  r0, r0, 28    cmpwi   cr1, r0, 9    ble     cr1, digIsNum    addic   r0, r0, 55    b       nextDigdigIsNum:    addic   r0, r0, 48nextDig:    stb     r0, 0(r10)          /* write to transmit reg */    eieio    addic.  r9, r9, -4    bge     OutDig    blr/* * print 3 digits hdec value to COM1 in polling mode * (r10=COM1 port, r3=val, r7=x00, r8=x0, r9=x, r0, r6=scratch) */OutDec:    li      r6, 10    divwu   r0, r3, r6          /* r0 = r3 / 10, r9 = r3 mod 10 */    mullw   r10, r0, r6    subf    r9, r10, r3    mr      r3, r0    divwu   r0, r3, r6          /* r0 = r3 / 10, r8 = r3 mod 10 */    mullw   r10, r0, r6    subf    r8, r10, r3    mr      r3, r0    divwu   r0, r3, r6          /* r0 = r3 / 10, r7 = r3 mod 10 */    mullw   r10, r0, r6    subf    r7, r10, r3    lis     r10, CFG_NS16550_COM1@h /* COM1 base address*/    ori     r10, r10, CFG_NS16550_COM1@l    or.     r7, r7, r7    bne     noblank1    li      r3, 0x20    b       OutDec4noblank1:    addi    r3, r7, 48          /* convert to ASCII */OutDec4:    lbz     r0, 0(r29)          /* slow down dummy read */    lbz     r0, 5(r10)          /* read link status */    eieio    andi.   r0, r0, 0x40        /* mask transmitter empty bit */    beq     cr0, OutDec4    stb     r3, 0(r10)          /* x00 to transmit */    eieio    or.     r7, r7, r8    beq     OutDec5    addi    r3, r8, 48          /* convert to ASCII */OutDec5:    lbz     r0, 0(r29)          /* slow down dummy read */    lbz     r0, 5(r10)          /* read link status */    eieio    andi.   r0, r0, 0x40        /* mask transmitter empty bit */    beq     cr0, OutDec5    stb     r3, 0(r10)          /* x0  to transmit */    eieio    addi    r3, r9, 48          /* convert to ASCII */OutDec6:    lbz     r0, 0(r29)          /* slow down dummy read */    lbz     r0, 5(r10)          /* read link status */    eieio    andi.   r0, r0, 0x40        /* mask transmitter empty bit */    beq     cr0, OutDec6    stb     r3, 0(r10)          /* x   to transmit */    eieio    blr/* * hang endless loop */toggleError:                    /* fail type in r6, r7=0xff, toggle LEDs */    stb     r7, 2(r30)          /* r7 to LED */    li      r0, 0    lis     r9, 127    ori     r9, r9, 65535toggleError1:    addic   r0, r0, 1    cmpw    cr1, r0, r9    ble     cr1, toggleError1    stb     r6, 2(r30)          /* r6 to LED */    li      r0, 0    lis     r9, 127    ori     r9, r9, 65535toggleError2:    addic   r0, r0, 1    cmpw    cr1, r0, r9    ble     cr1, toggleError2    b       toggleError/* * routines to read from ram spd */spdWaitIdle:    lis     r0, 0x1             /* timeout for about 100us */    mtctr   r0iSpd:    lbz     r10, 12(r14)    andi.   r10, r10, 0x20      /* mask and test MBB */    beq     idle    bdnz    iSpd    orc.    r10, r0, r0         /* return -1 to caller */idle:    bclr    20, 0               /* return to caller */waitSpd:    lis     r0, 0x10            /* timeout for about 1.5ms */    mtctr   r0wSpd:    lbz     r10, 12(r14)    andi.   r10, r10, 0x82    cmpli   0, 0, r10, 0x82     /* test MCF and MIF set */    beq     wend    bdnz    wSpd    orc.    r10, r0, r0         /* return -1 to caller */    bclr    20, 0               /* return to caller */wend:    li      r10, 0    stb     r10, 12(r14)        /* clear status */    bclr    20, 0               /* return to caller *//* * spdread * in:  r3 adr to read * out: r3 val or -1 for error * uses r10, assumes that r14 points to I2C controller */spdRead:    mfspr   r25, 8              /* save link register */    bl      spdWaitIdle    bne     spdErr    li      r10, 0x80           /* start with MEN */    stb     r10, 8(r14)    eieio    li      r10, 0xb0           /* start as master */    stb     r10, 8(r14)    eieio    li      r10, 0xa0           /* write device 0xA0 */    stb     r10, 16(r14)    eieio    bl      waitSpd    bne     spdErr    lbz     r10, 12(r14)        /* test ACK */    andi.   r10, r10, 0x01    bne     gotNoAck    stb     r3, 16(r14)         /* data address */    eieio    bl      waitSpd    bne     spdErr    li      r10, 0xb4           /* switch to read - restart */    stb     r10, 8(r14)    eieio    li      r10, 0xa1           /* read device 0xA0 */    stb     r10, 16(r14)    eieio    bl      waitSpd    bne     spdErr    li      r10, 0xa8           /* no ACK */    stb     r10, 8(r14)    eieio    lbz     r10, 16(r14)        /* trigger read next byte */    eieio    bl      waitSpd    bne     spdErr    li      r10, 0x88           /* generate STOP condition */    stb     r10, 8(r14)    eieio    lbz     r3, 16(r14)         /* return read byte */    mtspr   8, r25              /* restore link register */    blrgotNoAck:    li      r10, 0x80           /* generate STOP condition */    stb     r10, 8(r14)    eieiospdErr:    orc     r3, r0, r0          /* return -1 */    mtspr   8, r25              /* restore link register */    blrget_lnk_reg:    mflr    r3                  /* return link reg */    blrMessageBlock:MinitLogo:    .ascii  "\015\012*** ELTEC Elektronik, Mainz ***\015\012"    .ascii  "\015\012Initialising RAM\015\012\000"Mspd01:    .ascii  "       Reading SPD of SODIMM ...... \000"MramTyp:    .ascii  "\015\012\SDRAM with CL=2 at 100 MHz required!\015\012\000"MramConfErr:    .ascii  "\015\012\Unsupported SODIMM Configuration!\015\012\000"Mactivate:    .ascii  "       Activating \000"Mact0123e:    .ascii  " MByte.\015\012\000"Mok:    .ascii  "OK \015\012\000"Mfail:    .ascii  "FAILED \015\012\000"MnewLine:    .ascii  "\015\012\000"    .align 4