__S0 2100 0
__S1 190 0
_main 7DD 0 CODE
_exit 4 0 CODE
start 4 0 CODE
__Hintsave_0 190 0
__Lintsave_0 190 0
__Hintcode 4 0 CODE
__Lintcode 4 0 CODE
__Hintsave_1 190 0
__Lintsave_1 190 0
__Hintsave_2 190 0
__Lintsave_2 190 0
__Hintsave 190 0
__Lintsave 190 0
__Hintsave_3 190 0
__Lintsave_3 190 0
__Hcode 190 0
__Lcode 190 0
__Hstrings 8 0 STRING
__Lstrings 8 0 STRING
?a_main 20 0 BANK0
__Htemp 70 0 BANK0
__Ltemp 70 0 BANK0
__Hinit 4 0 CODE
__Linit 4 0 CODE
powerup 0 0 CODE
__Htext 190 0
__Ltext 190 0
__Hpowerup 4 0 CODE
__Lpowerup 0 0 CODE
__Hvectors 8 0 CODE
__Lvectors 8 0 CODE
__Hclrtext 8 0 CODE
__Lclrtext 8 0 CODE
__Hidloc 2000 0 IDLOC
__Lidloc 2000 0 IDLOC
__Hpstrings 8 0 CODE
__Lpstrings 8 0 CODE
__Hend_init 8 0 CODE
__Lend_init 4 0 CODE
__Hnvram 25 0 BANK0
__Lnvram 25 0 BANK0
__Hfloat_text0 8 0 CODE
__Lfloat_text0 8 0 CODE
__Hinit23 4 0 CODE
__Linit23 4 0 CODE
__Hfloat_text1 8 0 CODE
__Lfloat_text1 8 0 CODE
__Brbit_0 20 FFFFFF20 BANK0
__Hrbit_0 100 FFFFFF20 BANK0
__Lrbit_0 100 FFFFFF20 BANK0
__Brbit_1 A0 FFFFFBA0 BANK1
__Hrbss_0 25 0 BANK0
__Hrbit_1 500 FFFFFBA0 BANK1
__Lrbss_0 20 0 BANK0
__Lrbit_1 500 FFFFFBA0 BANK1
__Brbit_2 110 FFFFF890 BANK2
__Hrbss_1 A0 0 BANK1
__Hrbit_2 880 FFFFF890 BANK2
__Lrbss_1 A0 0 BANK1
__Lrbit_2 880 FFFFF890 BANK2
__Brbit_3 190 FFFFF510 BANK3
__Hrbss_2 110 0 BANK2
__Hrbit_3 C80 FFFFF510 BANK3
__Lrbss_2 110 0 BANK2
__Lrbit_3 C80 FFFFF510 BANK3
__Hrbss_3 190 0 BANK3
__Lrbss_3 190 0 BANK3
__Hintentry 4 0 CODE
__Lintentry 4 0 CODE
intlevel0 4 0 CODE
intlevel1 4 0 CODE
__Hfloat_text2 8 0 CODE
__Lfloat_text2 8 0 CODE
_Delay1Ms 775 0 CODE
__Hconfig 2007 0 CONFIG
__Lconfig 2007 0 CONFIG
__Hfloat_text3 8 0 CODE
__Lfloat_text3 8 0 CODE
__Hintret 4 0 CODE
__Lintret 4 0 CODE
__Hstruct 25 0 BANK0
__Lstruct 25 0 BANK0
__Hfloat_text4 8 0 CODE
__Lfloat_text4 8 0 CODE
__Hcommon_ram 190 0
__Lcommon_ram 190 0
__Hidata_0 8 0 CODE
__Lidata_0 8 0 CODE
__Hrdata_0 25 0 BANK0
__Lrdata_0 25 0 BANK0
__Hidata_1 8 0 CODE
__Lidata_1 8 0 CODE
__Heeprom_data 2100 0 EEDATA
__Leeprom_data 2100 0 EEDATA
__Hrdata_1 A0 0 BANK1
__Lrdata_1 A0 0 BANK1
__Hidata_2 8 0 CODE
__Lidata_2 8 0 CODE
__Hrdata_2 110 0 BANK2
__Lrdata_2 110 0 BANK2
__Hidata_3 8 0 CODE
__Lidata_3 8 0 CODE
__Hrdata_3 190 0 BANK3
__Lrdata_3 190 0 BANK3
__Hnvram_1 A0 0 BANK1
__Lnvram_1 A0 0 BANK1
__Bnvbit_0 25 FFFFFEFD BANK0
__Hnvbit_0 128 FFFFFEFD BANK0
__Lnvbit_0 128 FFFFFEFD BANK0
__Hnvram_2 110 0 BANK2
__Lnvram_2 110 0 BANK2
__Bnvbit_1 A0 FFFFFBA0 BANK1
__Hnvbit_1 500 FFFFFBA0 BANK1
__Lnvbit_1 500 FFFFFBA0 BANK1
__Hnvram_3 190 0 BANK3
__Lnvram_3 190 0 BANK3
__Bnvbit_2 110 FFFFF890 BANK2
__Hnvbit_2 880 FFFFF890 BANK2
__Lnvbit_2 880 FFFFF890 BANK2
__Bnvbit_3 190 FFFFF510 BANK3
__Hnvbit_3 C80 FFFFF510 BANK3
__Lnvbit_3 C80 FFFFF510 BANK3
__Hstringtable 8 0 ENTRY
__Lstringtable 8 0 ENTRY
?a_Delay1Ms 23 0 BANK0
__H__Z79926RS_ 190 0
__L__Z79926RS_ 190 0
%segments
powerup 0 7 CODE
intentry 8 F CODE
rbit_0 100 104 BANK0
text0 EEA FFF CODE
%locals
F:\experiment\ADC\delay-2\delay-2.obj
status 3
F:\experiment\ADC\delay-2\delay-2.c
15 775 0 CODE
17 775 0 CODE
19 77A 0 CODE
21 77B 0 CODE
22 785 0 CODE
23 78F 0 CODE
24 799 0 CODE
25 7A3 0 CODE
26 7AD 0 CODE
27 7B7 0 CODE
28 7C1 0 CODE
29 7CB 0 CODE
19 7D5 0 CODE
17 7DA 0 CODE
41 7DD 0 CODE
49 7DD 0 CODE
50 7E1 0 CODE
53 7E3 0 CODE
55 7E5 0 CODE
56 7E6 0 CODE
57 7E7 0 CODE
60 7E8 0 CODE
61 7E9 0 CODE
65 7EB 0 CODE
66 7ED 0 CODE
67 7EF 0 CODE
68 7F1 0 CODE
69 7F3 0 CODE
70 7F5 0 CODE
71 7F7 0 CODE
72 7F9 0 CODE
73 7FB 0 CODE
74 7FD 0 CODE
45 7FF 0 CODE