#define XPAR_GPIO_0_DEVICE_ID       110        /* Device ID for instance */#define XPAR_GPIO_0_BASEADDR        0x90000000 /* Register base address */#define XPAR_GPIO_0_INTERRUPT_PRESENT   0      /* Interrupts supported? */#define XPAR_GPIO_0_IS_DUAL             0      /* Dual channels supported? *//***************************************************************************** * * EMC defines. * DeviceID starts at 120 */#define XPAR_XEMC_NUM_INSTANCES     1#define XPAR_EMC_0_DEVICE_ID       120         /* Device ID for instance */#define XPAR_EMC_0_BASEADDR        0xE0000000  /* Register base address */#define XPAR_EMC_0_NUM_BANKS_MEM   3           /* Number of banks *//***************************************************************************** * * PLB Arbiter defines. * DeviceID starts at 130 */#define XPAR_XPLBARB_NUM_INSTANCES     1#define XPAR_PLBARB_0_DEVICE_ID       130         /* Device ID for instance */#define XPAR_PLBARB_0_BASEADDR        0x300       /* Register base address */#define XPAR_PLBARB_0_NUM_MASTERS     1           /* Number of masters on bus *//***************************************************************************** * * PLB To OPB Bridge defines. * DeviceID starts at 140 */#define XPAR_XPLB2OPB_NUM_INSTANCES     1#define XPAR_PLB2OPB_0_DEVICE_ID       140         /* Device ID for instance */#define XPAR_PLB2OPB_0_DCR_BASEADDR    0x0         /* DCR Register base address */#define XPAR_PLB2OPB_0_NUM_MASTERS       1         /* Number of masters on bus *//***************************************************************************** * * OPB To PLB Bridge defines. * DeviceID starts at 150 */#define XPAR_XOPB2PLB_NUM_INSTANCES     1#define XPAR_XOPB2PLB_ANY_OPB_REG_INTF       /* Accessible from OPB, not DCR */#define XPAR_OPB2PLB_0_DEVICE_ID       150   /* Device ID for instance */#define XPAR_OPB2PLB_0_OPB_BASEADDR    0x0   /* Register base address */#define XPAR_OPB2PLB_0_DCR_BASEADDR    0x0   /* DCR Register base address *//***************************************************************************** * * System ACE defines. * DeviceID starts at 160 */#define XPAR_XSYSACE_NUM_INSTANCES    1#define XPAR_SYSACE_0_DEVICE_ID       160         /* Device ID for instance */#define XPAR_SYSACE_0_BASEADDR        0xCF000000  /* Register base address *//***************************************************************************** * * HDLC defines. * DeviceID starts at 170 */#define XPAR_XHDLC_NUM_INSTANCES     1#define XPAR_HDLC_0_DEVICE_ID       170             /* Device ID for instance */#define XPAR_HDLC_0_BASEADDR        0x60010000      /* Register base address */#define XPAR_HDLC_0_TX_MEM_DEPTH    2048            /* Tx FIFO depth (bytes) */#define XPAR_HDLC_0_RX_MEM_DEPTH    2048            /* Rx FIFO depth (bytes) */#define XPAR_HDLC_0_DMA_PRESENT     3               /* DMA SG in hardware *//***************************************************************************** * * PS2 Reference driver defines. * DeviceID starts at 180 */#define XPAR_XPS2_NUM_INSTANCES    2#define XPAR_PS2_0_DEVICE_ID       180             /* Device ID for instance */#define XPAR_PS2_0_BASEADDR        0x40010000      /* Register base address */#define XPAR_PS2_1_DEVICE_ID       181             /* Device ID for instance */#define XPAR_PS2_1_BASEADDR        0x40020000      /* Register base address *//***************************************************************************** * * Rapid IO defines. * DeviceID starts at 190 */#define XPAR_XRAPIDIO_NUM_INSTANCES    1#define XPAR_RAPIDIO_0_DEVICE_ID       190             /* Device ID for instance */#define XPAR_RAPIDIO_0_BASEADDR        0x60000000      /* Register base address *//***************************************************************************** * * PCI defines. * DeviceID starts at 200 */#define XPAR_XPCI_NUM_INSTANCES                      1#define XPAR_OPB_PCI_1_DEVICE_ID                     200#define XPAR_OPB_PCI_1_BASEADDR                      0x86000000#define XPAR_OPB_PCI_1_HIGHADDR                      0x860001FF#define XPAR_OPB_PCI_1_PCIBAR_0                      0x10000000#define XPAR_OPB_PCI_1_PCIBAR_LEN_0                  27#define XPAR_OPB_PCI_1_PCIBAR2IPIF_0                 0xF0000000#define XPAR_OPB_PCI_1_PCIBAR_ENDIAN_TRANSLATE_EN_0  0#define XPAR_OPB_PCI_1_PCI_PREFETCH_0                1#define XPAR_OPB_PCI_1_PCI_SPACETYPE_0               1#define XPAR_OPB_PCI_1_PCIBAR_1                      0x3F000000#define XPAR_OPB_PCI_1_PCIBAR_LEN_1                  15#define XPAR_OPB_PCI_1_PCIBAR2IPIF_1                 0xC0FF8000#define XPAR_OPB_PCI_1_PCIBAR_ENDIAN_TRANSLATE_EN_1  0#define XPAR_OPB_PCI_1_PCI_PREFETCH_1                1#define XPAR_OPB_PCI_1_PCI_SPACETYPE_1               1#define XPAR_OPB_PCI_1_PCIBAR_2                      0x5F000000#define XPAR_OPB_PCI_1_PCIBAR_LEN_2                  16#define XPAR_OPB_PCI_1_PCIBAR2IPIF_2                 0x00000000#define XPAR_OPB_PCI_1_PCIBAR_ENDIAN_TRANSLATE_EN_2  0#define XPAR_OPB_PCI_1_PCI_PREFETCH_2                1#define XPAR_OPB_PCI_1_PCI_SPACETYPE_2               1#define XPAR_OPB_PCI_1_IPIFBAR_0                     0x80000000#define XPAR_OPB_PCI_1_IPIF_HIGHADDR_0               0x81FFFFFF#define XPAR_OPB_PCI_1_IPIFBAR2PCI_0                 0xF0000000#define XPAR_OPB_PCI_1_IPIFBAR_ENDIAN_TRANSLATE_EN_0 0#define XPAR_OPB_PCI_1_IPIF_PREFETCH_0               1#define XPAR_OPB_PCI_1_IPIF_SPACETYPE_0              1#define XPAR_OPB_PCI_1_IPIFBAR_1                     0x82000000#define XPAR_OPB_PCI_1_IPIF_HIGHADDR_1               0x820007FF#define XPAR_OPB_PCI_1_IPIFBAR2PCI_1                 0xCE000000#define XPAR_OPB_PCI_1_IPIFBAR_ENDIAN_TRANSLATE_EN_1 0#define XPAR_OPB_PCI_1_IPIF_PREFETCH_1               1#define XPAR_OPB_PCI_1_IPIF_SPACETYPE_1              1#define XPAR_OPB_PCI_1_IPIFBAR_2                     0x82320000#define XPAR_OPB_PCI_1_IPIF_HIGHADDR_2               0x8232FFFF#define XPAR_OPB_PCI_1_IPIFBAR2PCI_2                 0x00010000#define XPAR_OPB_PCI_1_IPIFBAR_ENDIAN_TRANSLATE_EN_2 0#define XPAR_OPB_PCI_1_IPIF_PREFETCH_2               1#define XPAR_OPB_PCI_1_IPIF_SPACETYPE_2              1#define XPAR_OPB_PCI_1_IPIFBAR_3                     0x82330000#define XPAR_OPB_PCI_1_IPIF_HIGHADDR_3               0x8233FFFF#define XPAR_OPB_PCI_1_IPIFBAR2PCI_3                 0x00010000#define XPAR_OPB_PCI_1_IPIFBAR_ENDIAN_TRANSLATE_EN_3 0#define XPAR_OPB_PCI_1_IPIF_PREFETCH_3               1#define XPAR_OPB_PCI_1_IPIF_SPACETYPE_3              0#define XPAR_OPB_PCI_1_IPIFBAR_4                     0x82340000#define XPAR_OPB_PCI_1_IPIF_HIGHADDR_4               0x8234FFFF#define XPAR_OPB_PCI_1_IPIFBAR2PCI_4                 0x00010000#define XPAR_OPB_PCI_1_IPIFBAR_ENDIAN_TRANSLATE_EN_4 0#define XPAR_OPB_PCI_1_IPIF_PREFETCH_4               0#define XPAR_OPB_PCI_1_IPIF_SPACETYPE_4              0#define XPAR_OPB_PCI_1_IPIFBAR_5                     0x82350000#define XPAR_OPB_PCI_1_IPIF_HIGHADDR_5               0x8235FFFF#define XPAR_OPB_PCI_1_IPIFBAR2PCI_5                 0x00010000#define XPAR_OPB_PCI_1_IPIFBAR_ENDIAN_TRANSLATE_EN_5 0#define XPAR_OPB_PCI_1_IPIF_PREFETCH_5               1#define XPAR_OPB_PCI_1_IPIF_SPACETYPE_5              1#define XPAR_OPB_PCI_1_DMA_BASEADDR                  0x87000000#define XPAR_OPB_PCI_1_DMA_HIGHADDR                  0x8700007F#define XPAR_OPB_PCI_1_DMA_CHAN_TYPE                 0#define XPAR_OPB_PCI_1_DMA_LENGTH_WIDTH              11/***************************************************************************** * * GEmac defines. * DeviceID starts at 210 */#define XPAR_XGEMAC_NUM_INSTANCES    1#define XPAR_GEMAC_0_DEVICE_ID       210#define XPAR_GEMAC_0_BASEADDR        0x61000000#define XPAR_GEMAC_0_DMA_TYPE        9#define XPAR_GEMAC_0_MIIM_EXIST      0#define XPAR_GEMAC_0_INCLUDE_STATS   0/***************************************************************************** * * Touchscreen defines . * DeviceID starts at 220 */#define XPAR_XTOUCHSCREEN_NUM_INSTANCES  1#define XPAR_TOUCHSCREEN_0_DEVICE_ID     220#define XPAR_TOUCHSCREEN_0_BASEADDR      0x70000000/***************************************************************************** * * DDR defines . * DeviceID starts at 230 */#define XPAR_XDDR_NUM_INSTANCES         1#define XPAR_DDR_0_DEVICE_ID            230#define XPAR_DDR_0_BASEADDR             0#define XPAR_DDR_0_INTERRUPT_PRESENT    0/***************************************************************************** * * EmacLite defines . * DeviceID starts at 240 */#define XPAR_XEMACLITE_NUM_INSTANCES    1#define XPAR_EMACLITE_0_DEVICE_ID       240#define XPAR_EMACLITE_0_BASEADDR        0#define XPAR_EMACLITE_0_TX_PING_PONG    0#define XPAR_EMACLITE_0_RX_PING_PONG    0/***************************************************************************** * * DSDAC defines . * DeviceID starts at 250 */#define XPAR_XDSDAC_NUM_INSTANCES       1#define XPAR_DSDAC_0_DEVICE_ID          250#define XPAR_DSDAC_0_BASEADDR           0/***************************************************************************** * * DSADC defines . * DeviceID starts at 260 */#define XPAR_XDSADC_NUM_INSTANCES       1#define XPAR_DSADC_0_DEVICE_ID          260#define XPAR_DSADC_0_BASEADDR           0/***************************************************************************** * * PCI Arbiter defines. * DeviceID starts at 270 */#define XPAR_XPCIARB_NUM_INSTANCES     1#define XPAR_OPB_PCI_ARBITER_0_DEVICE_ID     270#define XPAR_OPB_PCI_ARBITER_0_BASEADDR      0#define XPAR_OPB_PCI_ARBITER_0_NUM_PCI_MSTRS 2/**************************** Type Definitions *******************************//***************** Macros (Inline Functions) Definitions *********************/#endif              /* end of protection macro */