-------------------------------------------------------------------------------
-- lmb_bram_elaborate.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

library UNISIM;
use UNISIM.VCOMPONENTS.ALL;

entity lmb_bram_elaborate is
  generic (
    C_MEMSIZE : integer;
    C_PORT_DWIDTH : integer;
    C_PORT_AWIDTH : integer;
    C_NUM_WE : integer;
    C_FAMILY : string
    );
  port (
    BRAM_Rst_A : in std_logic;
    BRAM_Clk_A : in std_logic;
    BRAM_EN_A : in std_logic;
    BRAM_WEN_A : in std_logic_vector(0 to C_NUM_WE-1);
    BRAM_Addr_A : in std_logic_vector(0 to C_PORT_AWIDTH-1);
    BRAM_Din_A : out std_logic_vector(0 to C_PORT_DWIDTH-1);
    BRAM_Dout_A : in std_logic_vector(0 to C_PORT_DWIDTH-1);
    BRAM_Rst_B : in std_logic;
    BRAM_Clk_B : in std_logic;
    BRAM_EN_B : in std_logic;
    BRAM_WEN_B : in std_logic_vector(0 to C_NUM_WE-1);
    BRAM_Addr_B : in std_logic_vector(0 to C_PORT_AWIDTH-1);
    BRAM_Din_B : out std_logic_vector(0 to C_PORT_DWIDTH-1);
    BRAM_Dout_B : in std_logic_vector(0 to C_PORT_DWIDTH-1)
  );
end lmb_bram_elaborate;

architecture STRUCTURE of lmb_bram_elaborate is

  attribute WRITE_MODE_A : string;
  attribute WRITE_MODE_B : string;
  attribute READ_WIDTH_A : integer;
  attribute READ_WIDTH_B : integer;
  attribute WRITE_WIDTH_A : integer;
  attribute WRITE_WIDTH_B : integer;
  attribute RAM_EXTENSION_A : string;
  attribute RAM_EXTENSION_B : string;

  component RAMB16 is
    generic (
      WRITE_MODE_A : string;
      WRITE_MODE_B : string;
      READ_WIDTH_A : integer;
      READ_WIDTH_B : integer;
      WRITE_WIDTH_A : integer;
      WRITE_WIDTH_B : integer;
      RAM_EXTENSION_A : string;
      RAM_EXTENSION_B : string
    );
    port (
      ADDRA : in std_logic_vector(14 downto 0);
      CASCADEINA : in std_logic;
      CASCADEOUTA : out std_logic;
      CLKA : in std_logic;
      DIA : in std_logic_vector(31 downto 0);
      DIPA : in std_logic_vector(3 downto 0);
      DOA : out std_logic_vector(31 downto 0);
      DOPA : out std_logic_vector(3 downto 0);
      ENA : in std_logic;
      REGCEA : in std_logic;
      SSRA : in std_logic;
      WEA : in std_logic_vector(3 downto 0);
      ADDRB : in std_logic_vector(14 downto 0);
      CASCADEINB : in std_logic;
      CASCADEOUTB : out std_logic;
      CLKB : in std_logic;
      DIB : in std_logic_vector(31 downto 0);
      DIPB : in std_logic_vector(3 downto 0);
      DOB : out std_logic_vector(31 downto 0);
      DOPB : out std_logic_vector(3 downto 0);
      ENB : in std_logic;
      REGCEB : in std_logic;
      SSRB : in std_logic;
      WEB : in std_logic_vector(3 downto 0)
    );
  end component;

  attribute WRITE_MODE_A of RAMB16: component is "WRITE_FIRST";
  attribute WRITE_MODE_B of RAMB16: component is "WRITE_FIRST";
  attribute READ_WIDTH_A of RAMB16: component is 9;
  attribute READ_WIDTH_B of RAMB16: component is 9;
  attribute WRITE_WIDTH_A of RAMB16: component is 9;
  attribute WRITE_WIDTH_B of RAMB16: component is 9;
  attribute RAM_EXTENSION_A of RAMB16: component is "NONE";
  attribute RAM_EXTENSION_B of RAMB16: component is "NONE";

  -- Internal signals

  signal net_gnd0 : std_logic;
  signal net_gnd4 : std_logic_vector(3 downto 0);
  signal net_vcc0 : std_logic;
  signal pgassign1 : std_logic_vector(14 downto 0);
  signal pgassign10 : std_logic_vector(31 downto 0);
  signal pgassign11 : std_logic_vector(31 downto 0);
  signal pgassign12 : std_logic_vector(3 downto 0);
  signal pgassign13 : std_logic_vector(14 downto 0);
  signal pgassign14 : std_logic_vector(31 downto 0);
  signal pgassign15 : std_logic_vector(31 downto 0);
  signal pgassign16 : std_logic_vector(3 downto 0);
  signal pgassign17 : std_logic_vector(14 downto 0);
  signal pgassign18 : std_logic_vector(31 downto 0);
  signal pgassign19 : std_logic_vector(31 downto 0);
  signal pgassign2 : std_logic_vector(31 downto 0);
  signal pgassign20 : std_logic_vector(3 downto 0);
  signal pgassign21 : std_logic_vector(14 downto 0);
  signal pgassign22 : std_logic_vector(31 downto 0);
  signal pgassign23 : std_logic_vector(31 downto 0);
  signal pgassign24 : std_logic_vector(3 downto 0);
  signal pgassign25 : std_logic_vector(14 downto 0);
  signal pgassign26 : std_logic_vector(31 downto 0);
  signal pgassign27 : std_logic_vector(31 downto 0);
  signal pgassign28 : std_logic_vector(3 downto 0);
  signal pgassign29 : std_logic_vector(14 downto 0);
  signal pgassign3 : std_logic_vector(31 downto 0);
  signal pgassign30 : std_logic_vector(31 downto 0);
  signal pgassign31 : std_logic_vector(31 downto 0);
  signal pgassign32 : std_logic_vector(3 downto 0);
  signal pgassign33 : std_logic_vector(0 downto 0);
  signal pgassign34 : std_logic_vector(2 downto 0);
  signal pgassign35 : std_logic_vector(23 downto 0);
  signal pgassign4 : std_logic_vector(3 downto 0);
  signal pgassign5 : std_logic_vector(14 downto 0);
  signal pgassign6 : std_logic_vector(31 downto 0);
  signal pgassign7 : std_logic_vector(31 downto 0);
  signal pgassign8 : std_logic_vector(3 downto 0);
  signal pgassign9 : std_logic_vector(14 downto 0);

begin

  -- Internal assignments

  pgassign33(0 downto 0) <= B"1";
  pgassign34(2 downto 0) <= B"000";
  pgassign35(23 downto 0) <= B"000000000000000000000000";
  pgassign1(14 downto 14) <= B"1";
  pgassign1(13 downto 3) <= BRAM_Addr_A(19 to 29);
  pgassign1(2 downto 0) <= B"000";
  pgassign2(31 downto 8) <= B"000000000000000000000000";
  pgassign2(7 downto 0) <= BRAM_Dout_A(0 to 7);
  BRAM_Din_A(0 to 7) <= pgassign3(7 downto 0);
  pgassign4(3 downto 3) <= BRAM_WEN_A(0 to 0);
  pgassign4(2 downto 2) <= BRAM_WEN_A(0 to 0);
  pgassign4(1 downto 1) <= BRAM_WEN_A(0 to 0);
  pgassign4(0 downto 0) <= BRAM_WEN_A(0 to 0);
  pgassign5(14 downto 14) <= B"1";
  pgassign5(13 downto 3) <= BRAM_Addr_B(19 to 29);
  pgassign5(2 downto 0) <= B"000";
  pgassign6(31 downto 8) <= B"000000000000000000000000";
  pgassign6(7 downto 0) <= BRAM_Dout_B(0 to 7);
  BRAM_Din_B(0 to 7) <= pgassign7(7 downto 0);
  pgassign8(3 downto 3) <= BRAM_WEN_B(0 to 0);
  pgassign8(2 downto 2) <= BRAM_WEN_B(0 to 0);
  pgassign8(1 downto 1) <= BRAM_WEN_B(0 to 0);
  pgassign8(0 downto 0) <= BRAM_WEN_B(0 to 0);
  pgassign9(14 downto 14) <= B"1";
  pgassign9(13 downto 3) <= BRAM_Addr_A(19 to 29);
  pgassign9(2 downto 0) <= B"000";
  pgassign10(31 downto 8) <= B"000000000000000000000000";
  pgassign10(7 downto 0) <= BRAM_Dout_A(8 to 15);
  BRAM_Din_A(8 to 15) <= pgassign11(7 downto 0);
  pgassign12(3 downto 3) <= BRAM_WEN_A(1 to 1);
  pgassign12(2 downto 2) <= BRAM_WEN_A(1 to 1);
  pgassign12(1 downto 1) <= BRAM_WEN_A(1 to 1);
  pgassign12(0 downto 0) <= BRAM_WEN_A(1 to 1);
  pgassign13(14 downto 14) <= B"1";
  pgassign13(13 downto 3) <= BRAM_Addr_B(19 to 29);
  pgassign13(2 downto 0) <= B"000";
  pgassign14(31 downto 8) <= B"000000000000000000000000";
  pgassign14(7 downto 0) <= BRAM_Dout_B(8 to 15);
  BRAM_Din_B(8 to 15) <= pgassign15(7 downto 0);
  pgassign16(3 downto 3) <= BRAM_WEN_B(1 to 1);
  pgassign16(2 downto 2) <= BRAM_WEN_B(1 to 1);
  pgassign16(1 downto 1) <= BRAM_WEN_B(1 to 1);
  pgassign16(0 downto 0) <= BRAM_WEN_B(1 to 1);
  pgassign17(14 downto 14) <= B"1";
  pgassign17(13 downto 3) <= BRAM_Addr_A(19 to 29);
  pgassign17(2 downto 0) <= B"000";
  pgassign18(31 downto 8) <= B"000000000000000000000000";
  pgassign18(7 downto 0) <= BRAM_Dout_A(16 to 23);
  BRAM_Din_A(16 to 23) <= pgassign19(7 downto 0);
  pgassign20(3 downto 3) <= BRAM_WEN_A(2 to 2);
  pgassign20(2 downto 2) <= BRAM_WEN_A(2 to 2);
  pgassign20(1 downto 1) <= BRAM_WEN_A(2 to 2);
  pgassign20(0 downto 0) <= BRAM_WEN_A(2 to 2);
  pgassign21(14 downto 14) <= B"1";
  pgassign21(13 downto 3) <= BRAM_Addr_B(19 to 29);
  pgassign21(2 downto 0) <= B"000";
  pgassign22(31 downto 8) <= B"000000000000000000000000";
  pgassign22(7 downto 0) <= BRAM_Dout_B(16 to 23);
  BRAM_Din_B(16 to 23) <= pgassign23(7 downto 0);
  pgassign24(3 downto 3) <= BRAM_WEN_B(2 to 2);
  pgassign24(2 downto 2) <= BRAM_WEN_B(2 to 2);
  pgassign24(1 downto 1) <= BRAM_WEN_B(2 to 2);
  pgassign24(0 downto 0) <= BRAM_WEN_B(2 to 2);
  pgassign25(14 downto 14) <= B"1";
  pgassign25(13 downto 3) <= BRAM_Addr_A(19 to 29);
  pgassign25(2 downto 0) <= B"000";
  pgassign26(31 downto 8) <= B"000000000000000000000000";
  pgassign26(7 downto 0) <= BRAM_Dout_A(24 to 31);
  BRAM_Din_A(24 to 31) <= pgassign27(7 downto 0);
  pgassign28(3 downto 3) <= BRAM_WEN_A(3 to 3);
  pgassign28(2 downto 2) <= BRAM_WEN_A(3 to 3);
  pgassign28(1 downto 1) <= BRAM_WEN_A(3 to 3);
  pgassign28(0 downto 0) <= BRAM_WEN_A(3 to 3);
  pgassign29(14 downto 14) <= B"1";
  pgassign29(13 downto 3) <= BRAM_Addr_B(19 to 29);
  pgassign29(2 downto 0) <= B"000";
  pgassign30(31 downto 8) <= B"000000000000000000000000";
  pgassign30(7 downto 0) <= BRAM_Dout_B(24 to 31);
  BRAM_Din_B(24 to 31) <= pgassign31(7 downto 0);
  pgassign32(3 downto 3) <= BRAM_WEN_B(3 to 3);
  pgassign32(2 downto 2) <= BRAM_WEN_B(3 to 3);
  pgassign32(1 downto 1) <= BRAM_WEN_B(3 to 3);
  pgassign32(0 downto 0) <= BRAM_WEN_B(3 to 3);
  net_gnd0 <= '0';
  net_gnd4(3 downto 0) <= B"0000";
  net_vcc0 <= '1';

  ramb16_0 : RAMB16
    generic map (
      WRITE_MODE_A => "WRITE_FIRST",
      WRITE_MODE_B => "WRITE_FIRST",
      READ_WIDTH_A => 9,
      READ_WIDTH_B => 9,
      WRITE_WIDTH_A => 9,
      WRITE_WIDTH_B => 9,
      RAM_EXTENSION_A => "NONE",
      RAM_EXTENSION_B => "NONE"
    )
    port map (
      ADDRA => pgassign1,
      CASCADEINA => net_gnd0,
      CASCADEOUTA => open,
      CLKA => BRAM_Clk_A,
      DIA => pgassign2,
      DIPA => net_gnd4,
      DOA => pgassign3,
      DOPA => open,
      ENA => BRAM_EN_A,
      REGCEA => net_vcc0,
      SSRA => BRAM_Rst_A,
      WEA => pgassign4,
      ADDRB => pgassign5,
      CASCADEINB => net_gnd0,
      CASCADEOUTB => open,
      CLKB => BRAM_Clk_B,
      DIB => pgassign6,
      DIPB => net_gnd4,
      DOB => pgassign7,
      DOPB => open,
      ENB => BRAM_EN_B,
      REGCEB => net_vcc0,
      SSRB => BRAM_Rst_B,
      WEB => pgassign8
    );

  ramb16_1 : RAMB16
    generic map (
      WRITE_MODE_A => "WRITE_FIRST",
      WRITE_MODE_B => "WRITE_FIRST",
      READ_WIDTH_A => 9,
      READ_WIDTH_B => 9,
      WRITE_WIDTH_A => 9,
      WRITE_WIDTH_B => 9,
      RAM_EXTENSION_A => "NONE",
      RAM_EXTENSION_B => "NONE"
    )
    port map (
      ADDRA => pgassign9,
      CASCADEINA => net_gnd0,
      CASCADEOUTA => open,
      CLKA => BRAM_Clk_A,
      DIA => pgassign10,
      DIPA => net_gnd4,
      DOA => pgassign11,
      DOPA => open,
      ENA => BRAM_EN_A,
      REGCEA => net_vcc0,
      SSRA => BRAM_Rst_A,
      WEA => pgassign12,
      ADDRB => pgassign13,
      CASCADEINB => net_gnd0,
      CASCADEOUTB => open,
      CLKB => BRAM_Clk_B,
      DIB => pgassign14,
      DIPB => net_gnd4,
      DOB => pgassign15,
      DOPB => open,
      ENB => BRAM_EN_B,
      REGCEB => net_vcc0,
      SSRB => BRAM_Rst_B,
      WEB => pgassign16
    );

  ramb16_2 : RAMB16
    generic map (
      WRITE_MODE_A => "WRITE_FIRST",
      WRITE_MODE_B => "WRITE_FIRST",
      READ_WIDTH_A => 9,
      READ_WIDTH_B => 9,
      WRITE_WIDTH_A => 9,
      WRITE_WIDTH_B => 9,
      RAM_EXTENSION_A => "NONE",
      RAM_EXTENSION_B => "NONE"
    )
    port map (
      ADDRA => pgassign17,
      CASCADEINA => net_gnd0,
      CASCADEOUTA => open,
      CLKA => BRAM_Clk_A,
      DIA => pgassign18,
      DIPA => net_gnd4,
      DOA => pgassign19,
      DOPA => open,
      ENA => BRAM_EN_A,
      REGCEA => net_vcc0,
      SSRA => BRAM_Rst_A,
      WEA => pgassign20,
      ADDRB => pgassign21,
      CASCADEINB => net_gnd0,
      CASCADEOUTB => open,
      CLKB => BRAM_Clk_B,
      DIB => pgassign22,
      DIPB => net_gnd4,
      DOB => pgassign23,
      DOPB => open,
      ENB => BRAM_EN_B,
      REGCEB => net_vcc0,
      SSRB => BRAM_Rst_B,
      WEB => pgassign24
    );

  ramb16_3 : RAMB16
    generic map (
      WRITE_MODE_A => "WRITE_FIRST",
      WRITE_MODE_B => "WRITE_FIRST",
      READ_WIDTH_A => 9,
      READ_WIDTH_B => 9,
      WRITE_WIDTH_A => 9,
      WRITE_WIDTH_B => 9,
      RAM_EXTENSION_A => "NONE",
      RAM_EXTENSION_B => "NONE"
    )
    port map (
      ADDRA => pgassign25,
      CASCADEINA => net_gnd0,
      CASCADEOUTA => open,
      CLKA => BRAM_Clk_A,
      DIA => pgassign26,
      DIPA => net_gnd4,
      DOA => pgassign27,
      DOPA => open,
      ENA => BRAM_EN_A,
      REGCEA => net_vcc0,
      SSRA => BRAM_Rst_A,
      WEA => pgassign28,
      ADDRB => pgassign29,
      CASCADEINB => net_gnd0,
      CASCADEOUTB => open,
      CLKB => BRAM_Clk_B,
      DIB => pgassign30,
      DIPB => net_gnd4,
      DOB => pgassign31,
      DOPB => open,
      ENB => BRAM_EN_B,
      REGCEB => net_vcc0,
      SSRB => BRAM_Rst_B,
      WEB => pgassign32
    );

end architecture STRUCTURE;