Release 10.1.01 - xst K.34 (nt)Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.--> Parameter TMPDIR set to E:/download_material/virtex4_board/XTremeDSP_developmentIV/Examples/host_interface_basic/ise/host_interface/xst/projnav.tmpTotal REAL time to Xst completion: 0.00 secsTotal CPU time to Xst completion: 0.63 secs --> Parameter xsthdpdir set to E:/download_material/virtex4_board/XTremeDSP_developmentIV/Examples/host_interface_basic/ise/host_interface/xstTotal REAL time to Xst completion: 0.00 secsTotal CPU time to Xst completion: 0.63 secs --> Reading design: host_interface.prjTABLE OF CONTENTS  1) Synthesis Options Summary  2) HDL Compilation  3) Design Hierarchy Analysis  4) HDL Analysis  5) HDL Synthesis     5.1) HDL Synthesis Report  6) Advanced HDL Synthesis     6.1) Advanced HDL Synthesis Report  7) Low Level Synthesis  8) Partition Report  9) Final Report     9.1) Device utilization summary     9.2) Partition Resource Summary     9.3) TIMING REPORT=========================================================================*                      Synthesis Options Summary                        *=========================================================================---- Source ParametersInput File Name                    : "host_interface.prj"Input Format                       : mixedIgnore Synthesis Constraint File   : NO---- Target ParametersOutput File Name                   : "host_interface"Output Format                      : NGCTarget Device                      : xc4vsx35-10-ff668---- Source OptionsTop Module Name                    : host_interfaceAutomatic FSM Extraction           : YESFSM Encoding Algorithm             : AutoSafe Implementation                : NoFSM Style                          : lutRAM Extraction                     : YesRAM Style                          : AutoROM Extraction                     : YesMux Style                          : AutoDecoder Extraction                 : YESPriority Encoder Extraction        : YESShift Register Extraction          : YESLogical Shifter Extraction         : YESXOR Collapsing                     : YESROM Style                          : AutoMux Extraction                     : YESResource Sharing                   : YESAsynchronous To Synchronous        : NOUse DSP Block                      : autoAutomatic Register Balancing       : No---- Target OptionsAdd IO Buffers                     : YESGlobal Maximum Fanout              : 500Add Generic Clock Buffer(BUFG)     : 32Number of Regional Clock Buffers   : 24Register Duplication               : YESSlice Packing                      : YESOptimize Instantiated Primitives   : NOUse Clock Enable                   : AutoUse Synchronous Set                : AutoUse Synchronous Reset              : AutoPack IO Registers into IOBs        : autoEquivalent register Removal        : YES---- General OptionsOptimization Goal                  : SpeedOptimization Effort                : 1Power Reduction                    : NOLibrary Search Order               : host_interface.lsoKeep Hierarchy                     : NONetlist Hierarchy                  : as_optimizedRTL Output                         : YesGlobal Optimization                : AllClockNetsRead Cores                         : YESWrite Timing Constraints           : NOCross Clock Analysis               : NOHierarchy Separator                : /Bus Delimiter                      : <>Case Specifier                     : maintainSlice Utilization Ratio            : 100BRAM Utilization Ratio             : 100DSP48 Utilization Ratio            : 100Verilog 2001                       : YESAuto BRAM Packing                  : NOSlice Utilization Ratio Delta      : 5==================================================================================================================================================*                          HDL Compilation                              *=========================================================================Compiling vhdl file "E:/host_interface_basic/source/fifocnt4.vhd" in Library work.Entity <FIFOCNT4> compiled.Entity <FIFOCNT4> (Architecture <FIFOCNT4_arch>) compiled.Compiling vhdl file "E:/host_interface_basic/source/fwfrff_32.vhd" in Library work.Entity <FWFRFF_32> compiled.Entity <FWFRFF_32> (Architecture <FWFRFF_32_arch>) compiled.Compiling vhdl file "E:/host_interface_basic/source/ringregosc.vhd" in Library work.Entity <ringregosc> compiled.Entity <ringregosc> (Architecture <ringregosc>) compiled.Compiling vhdl file "E:/host_interface_basic/source/counter.vhd" in Library work.Entity <counter> compiled.Entity <counter> (Architecture <counter>) compiled.Compiling vhdl file "E:/host_interface_basic/source/if_main.vhd" in Library work.Entity <if_main> compiled.Entity <if_main> (Architecture <if_main_arch>) compiled.Compiling vhdl file "E:/host_interface_basic/source/dma_ctrl.vhd" in Library work.Entity <DMA_CTRL> compiled.Entity <DMA_CTRL> (Architecture <DMA_CTRL_arch>) compiled.Compiling vhdl file "E:/host_interface_basic/source/dcm_standby.vhd" in Library work.Entity <dcm_standby> compiled.Entity <dcm_standby> (Architecture <dcm_standby>) compiled.Compiling vhdl file "E:/download_material/virtex4_board/XTremeDSP_developmentIV/Examples/host_interface_basic/ise/host_interface/dimeclk_module_mod.vhd" in Library work.Entity <dimeclk_module> compiled.Entity <dimeclk_module> (Architecture <BEHAVIORAL>) compiled.Compiling vhdl file "E:/host_interface_basic/source/sv_iface.vhd" in Library work.Entity <SV_IFACE> compiled.Entity <SV_IFACE> (Architecture <SV_IFACE_arch>) compiled.Compiling vhdl file "E:/host_interface_basic/source/syncfifo.vhd" in Library work.Entity <SYNCFIFO> compiled.Entity <SYNCFIFO> (Architecture <SYNCFIFO_ARCH>) compiled.Compiling vhdl file "E:/host_interface_basic/source/host_interface.vhd" in Library work.Entity <host_interface> compiled.Entity <host_interface> (Architecture <host_interface_arch>) compiled.=========================================================================*                     Design Hierarchy Analysis                         *=========================================================================Analyzing hierarchy for entity <host_interface> in library <work> (architecture <host_interface_arch>).Analyzing hierarchy for entity <dimeclk_module> in library <work> (architecture <BEHAVIORAL>).Analyzing hierarchy for entity <SV_IFACE> in library <work> (architecture <SV_IFACE_arch>) with generics.	BLOCK_SIZEg = 4	NUM_BLOCKSg = 1	NUM_REGSg = 3Analyzing hierarchy for entity <SYNCFIFO> in library <work> (architecture <SYNCFIFO_ARCH>).Analyzing hierarchy for entity <dcm_standby> in library <work> (architecture <dcm_standby>).Analyzing hierarchy for entity <IF_MAIN> in library <work> (architecture <if_main_arch>) with generics.	BLOCK_SIZEg = 4	NUM_BLOCKSg = 1	NUM_REGSg = 3Analyzing hierarchy for entity <DMA_CTRL> in library <work> (architecture <DMA_CTRL_arch>).Analyzing hierarchy for entity <ringregosc> in library <work> (architecture <ringregosc>).Analyzing hierarchy for entity <counter> in library <work> (architecture <counter>).Analyzing hierarchy for entity <FWFRFF_32> in library <work> (architecture <FWFRFF_32_arch>) with generics.	ATLEASTNEMPTYg = 8	ATLEASTNFULLg = 8	NEEDBACKUPg = 0Analyzing hierarchy for entity <FIFOCNT4> in library <work> (architecture <FIFOCNT4_arch>).=========================================================================*                            HDL Analysis                               *=========================================================================Analyzing Entity <host_interface> in library <work> (Architecture <host_interface_arch>).WARNING:Xst:753 - "E:/host_interface_basic/source/host_interface.vhd" line 180: Unconnected output port 'CLKIN_IBUFG_OUT' of component 'dimeclk_module'.WARNING:Xst:753 - "E:/host_interface_basic/source/host_interface.vhd" line 197: Unconnected output port 'COUNT' of component 'SV_IFACE'.WARNING:Xst:753 - "E:/host_interface_basic/source/host_interface.vhd" line 197: Unconnected output port 'DMA_SEL' of component 'SV_IFACE'.WARNING:Xst:753 - "E:/host_interface_basic/source/host_interface.vhd" line 197: Unconnected output port 'RST' of component 'SV_IFACE'.WARNING:Xst:753 - "E:/host_interface_basic/source/host_interface.vhd" line 197: Unconnected output port 'DMA_RESET' of component 'SV_IFACE'.WARNING:Xst:753 - "E:/host_interface_basic/source/host_interface.vhd" line 233: Unconnected output port 'FIFO_FULL' of component 'SYNCFIFO'.WARNING:Xst:819 - "E:/host_interface_basic/source/host_interface.vhd" line 298: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:   <REG1>, <REG2>Entity <host_interface> analyzed. Unit <host_interface> generated.Analyzing Entity <dimeclk_module> in library <work> (Architecture <BEHAVIORAL>).WARNING:Xst:2211 - "E:/download_material/virtex4_board/XTremeDSP_developmentIV/Examples/host_interface_basic/ise/host_interface/dimeclk_module_mod.vhd" line 124: Instantiating black box module <IBUFG>.WARNING:Xst:753 - "E:/download_material/virtex4_board/XTremeDSP_developmentIV/Examples/host_interface_basic/ise/host_interface/dimeclk_module_mod.vhd" line 169: Unconnected output port 'CLK180' of component 'dcm_standby'.WARNING:Xst:753 - "E:/download_material/virtex4_board/XTremeDSP_developmentIV/Examples/host_interface_basic/ise/host_interface/dimeclk_module_mod.vhd" line 169: Unconnected output port 'CLK270' of component 'dcm_standby'.WARNING:Xst:753 - "E:/download_material/virtex4_board/XTremeDSP_developmentIV/Examples/host_interface_basic/ise/host_interface/dimeclk_module_mod.vhd" line 169: Unconnected output port 'CLK2X' of component 'dcm_standby'.WARNING:Xst:753 - "E:/download_material/virtex4_board/XTremeDSP_developmentIV/Examples/host_interface_basic/ise/host_interface/dimeclk_module_mod.vhd" line 169: Unconnected output port 'CLK2X180' of component 'dcm_standby'.WARNING:Xst:753 - "E:/download_material/virtex4_board/XTremeDSP_developmentIV/Examples/host_interface_basic/ise/host_interface/dimeclk_module_mod.vhd" line 169: Unconnected output port 'CLK90' of component 'dcm_standby'.WARNING:Xst:753 - "E:/download_material/virtex4_board/XTremeDSP_developmentIV/Examples/host_interface_basic/ise/host_interface/dimeclk_module_mod.vhd" line 169: Unconnected output port 'CLKDV' of component 'dcm_standby'.