eld			@rp0+d0, b
				erps		rp3+s1
				bnzd		r7, dp0_ch_30_tc_alloc_2
				eld			rp0, rp3				
				brad		dp0_loop_sblimit
				erps		rp3+s0



;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::;
;::::::::::::::::::::::::[  channel mode 2/2  ]::::::::::::::::::::::;
;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::;
dp0_channel_config_22
/*loop_start*/	eld			rp0, rp3
				ecld		a, r6
				eld			rp1, mc0
				erpn		rp1, a
				eld			a, @rp1						; the number of sbgr.
				eld			rp1, mc1
				erpn		rp1, a
				eld			a, @rp1						; tc_alloc[sbgr]
				ecld		r5, a
; check_tc_alloc
				cmp			eq, r5, #0					; tc_alloc
				brt			dp0_ch_22_tc_alloc_0 
				cmp			eq, r5, #1
				brt			dp0_ch_22_tc_alloc_1	
				cmp			eq, r5, #2
				brt			dp0_ch_22_tc_alloc_2	
				cmp			eq, r5, #3
				brt			dp0_ch_22_tc_alloc_3
.ifdef _DEBUG_
/** debug **/	bra			$
.endif

dp0_ch_22_tc_alloc_0
				eld			a, @rp0+s0
				eld			b, @rp0+s0
				eld			c, @rp0+s0
				esub		a, c, d, @rp0+s0
				esub		b, d
				erpn		rp0, #-(96*4)
				eld			@rp0+d0, a
				eld			@rp0+d0, b
				erps		rp3+s1
				bnzd		r7, dp0_ch_22_tc_alloc_0
				eld			rp0, rp3				
				brad		dp0_loop_sblimit
				erps		rp3+s0
dp0_ch_22_tc_alloc_1
				eld			a, @rp0+s0
				eld			b, @rp0+s0
				eld			c, @rp0+s0
				esub		a, c, d, @rp0+s0
				esub		b, d
				erpn		rp0, #-(96*4)
				eld			@rp0+d0, c
				eld			@rp0+d0, b
				eld			@rp0+d0, a
				erps		rp3+s1
				bnzd		r7, dp0_ch_22_tc_alloc_1
				eld			rp0, rp3				
				brad		dp0_loop_sblimit
				erps		rp3+s0
dp0_ch_22_tc_alloc_2
				eld			a, @rp0+s0
				eld			b, @rp0+s0
				eld			c, @rp0+s0
				esub		a, c, d, @rp0+s0
				esub		b, d
				erpn		rp0, #-(96*4)
				eld			@rp0+d0, a
				eld			@rp0+d0, d
				erpd		rp0+d0
				eld			@rp0+d0, b
				erps		rp3+s1
				bnzd		r7, dp0_ch_22_tc_alloc_2
				eld			rp0, rp3				
				brad		dp0_loop_sblimit
				erps		rp3+s0
dp0_ch_22_tc_alloc_3
				eld			a, @rp0+s0
				eld			b, @rp0+s0
				eld			c, @rp0+s0
				esub		a, c, d, @rp0+s0
				esub		b, d
				erpn		rp0, #-(96*4)
				eld			@rp0+d0, c
				eld			@rp0+d0, d
				eld			@rp0+d0, a
				eld			@rp0+d0, b
				erps		rp3+s1
				bnzd		r7, dp0_ch_22_tc_alloc_3
				eld			rp0, rp3				
				brad		dp0_loop_sblimit
				erps		rp3+s0



;;;>> loop control <<<====================================================				
dp0_loop_sblimit
				ld			r7, #PARTS-1
				inc			r6
				cmp			eq, r6, #SBLIMIT				; sblimit loop
				jpf			a13			
				
				erpn		rp3, #MAX_CHANNEL*PARTS*SBLIMIT-SBLIMIT
				ld			r6, #0
				dt			r8								; granules loop
				jpf			a13				
				jmp			_end_dematrixing_


;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::;
;::                                                                ::;
;::                       Dematrix procedure 2                     ::;
;::                                                                ::;
;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::;
dematrix_procedure_2
				esla		a
				esla		a
				ecld		r3, a
				ld			a13, #dematrix_process_table2
				add			a13, r3
				ldc			r1, @a13
				add			a13, #2
				ldc			r0, @a13
				ld			e13, r1
				ld			r13, r0
				jmp			a13
				

;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::;
;::::::::::::::::::::::::[  channel mode 3/2  ]::::::::::::::::::::::;
;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::;
dp2_channel_config_32
/*loop_start*/	eld			rp0, rp3
				ecld		a, r6
				eld			rp1, mc0
				erpn		rp1, a
				eld			a, @rp1						; the number of sbgr.
				eld			rp1, mc1
				erpn		rp1, a
				eld			a, @rp1						; tc_alloc[sbgr]
				ecld		r5, a
; check_tc_alloc
				cmp			eq, r5, #0					; tc_alloc
				brt			dp2_ch_32_tc_alloc_0 
				cmp			eq, r5, #1
				brt			dp2_ch_32_tc_alloc_1	
				cmp			eq, r5, #2
				brt			dp2_ch_32_tc_alloc_2	
				cmp			eq, r5, #3
				brt			dp2_ch_32_tc_alloc_3	
				cmp			eq, r5, #4
				brt			dp2_ch_32_tc_alloc_4 
				cmp			eq, r5, #5
				brt			dp2_ch_32_tc_alloc_5	
				cmp			eq, r5, #6
				brt			dp2_ch_32_tc_alloc_6	
				cmp			eq, r5, #7
				brt			dp2_ch_32_tc_alloc_7
.ifdef _DEBUG_
/** debug **/	bra			$
.endif
				
dp2_ch_32_tc_alloc_0
				eld			a, @rp0+s0
				eld			b, @rp0+s0
				eld			c, @rp0+s0
				esub		a, c, d, @rp0+s0 
				esub		b, c, c, @rp0+s0 
				eadd		d, c
				esra		d					; surround_sample
				eadd		a, d
				esub		b, d
				erpn		rp0, #-(96*5)
				eld			@rp0+d0, a
				eld			@rp0+d0, b
				erps		rp3+s1
				bnzd		r7, dp2_ch_32_tc_alloc_0
				eld			rp0, rp3				
				brad		dp2_loop_sblimit
				erps		rp3+s0
dp2_ch_32_tc_alloc_1
				eld			a, @rp0+s0
				eld			b, @rp0+s0
				eld			ma0, @rp0+s0
				eld			c, @rp0+s0
				esub		a, ma0, x0, @rp0+s0 
				eadd		c, x0
				esra		c					; surround_sample
				eadd		a, c
				esub		b, a
				esub		b, c
				erpn		rp0, #-(96*5)
				eld			@rp0+d0, ma0
				eld			@rp0+d0, b
				eld			@rp0+d0, a
				erps		rp3+s1
				bnzd		r7, dp2_ch_32_tc_alloc_1
				eld			rp0, rp3				
				brad		dp2_loop_sblimit
				erps		rp3+s0
dp2_ch_32_tc_alloc_2
				eld			a, @rp0+s0
				eld			b, @rp0+s0
				eld			ma0, @rp0+s0
				eld			c, @rp0+s0
				esub		b, ma0, x0, @rp0+s0 
				eadd		c, x0
				esra		c					; surround_sample
				esub		b, c
				esub		a, b
				eadd		a, c
				erpn		rp0, #-(96*5)
				eld			@rp0+d0, a
				eld			@rp0+d0, ma0
				eld			@rp0+d0, b
				erps		rp3+s1
				bnzd		r7, dp2_ch_32_tc_alloc_2
				eld			rp0, rp3				
				brad		dp2_loop_sblimit
				erps		rp3+s0
dp2_ch_32_tc_alloc_3
				eld			c, @rp0+s0
				eld			a, @rp0+s0
				eld			b, @rp0+s0
				eld			ma0, b
				esub		b, c, d, @rp0+s0 
				eadd		a, c, c, @rp0+s0  
				eadd		b, d
				esla		b
				esub		b, c
				esub		a, d
				esla		ma0
				esub		a, ma0
				erpn		rp0, #-(96*5)
				eld			@rp0+d0, d
				eld			@rp0+d0, a
				erpd		rp0+d0
				eld			@rp0+d0, b
				erps		rp3+s1
				bnzd		r7, dp2_ch_32_tc_alloc_3
				eld			rp0, rp3				
				brad		dp2_loop_sblimit
				erps		rp3+s0				
dp2_ch_32_tc_alloc_4
				eld			a, @rp0+s0
				eld			b, @rp0+s0
				eld			c, @rp0+s0
				eadd		a, b
				esub		b, c, d, @rp0+s0  
				esla		c
				esub		a, c, c, @rp0+s0  
				esub		a, c 
				esub		b, c
				esla		b
				esub		b, d
				erpn		rp0, #-(96*5)
				eld			@rp0+d0, a
				eld			@rp0+d0, c
				erpd		rp0+d0
				erpd		rp0+d0
				eld			@rp0+d0, b
				erps		rp3+s1
				bnzd		r7, dp2_ch_32_tc_alloc_4
				eld			rp0, rp3				
				brad		dp2_loop_sblimit
				erps		rp3+s0				
dp2_ch_32_tc_alloc_5
				eld			c, @rp0+s0
				eld			a, @rp0+s0
				erps		rp0+s0
				esub		a, c, c, @rp0+s0 
				eadd		a, c, d, @rp0+s0 
				esub		a, d
				esra		a
				erpn		rp0, #-(96*5)
				eld			@rp0+d0, c
				eld			@rp0+d0, d
				erpd		rp0+d0
				eld			@rp0+d0, a
				eld			@rp0+d0, a
				erps		rp3+s1
				bnzd		r7, dp2_ch_32_tc_alloc_5
				eld			rp0, rp3				
				brad		dp2_loop_sblimit
				erps		rp3+s0				
dp2_ch_32_tc_alloc_6
				eld			a, @rp0+s0
				eld			b, @rp0+s0
				eld			c, @rp0+s0
				eld			x0, b
				eld			x1, c
				esub		b, a
				esub		b, c, d, @rp0+s0 
				eadd		a, x0				
				esub		a, c, c, @rp0+s0				
				eadd		b, d
				esub		b, c
				esub		a, d
				esra		a
				erpn		rp0, #-(96*5)
				eld			@rp0+d0, d
				eld			@rp0+d0, x1
				eld			@rp0+d0, a
				eld			@rp0+d0, b
				erps		rp3+s1
				bnzd		r7, dp2_ch_32_tc_alloc_6
				eld			rp0, rp3				
				brad		dp2_loop_sblimit
				erps		rp3+s0				
dp2_ch_32_tc_alloc_7
				eld			a, @rp0+s0
				eld			b, @rp0+s0
				eld			c, @rp0+s0
				eld			x0, b
				eld			x1, c
				esub		b, a
				eadd		b, c, d, @rp0+s0 
				eadd		a, x0				
				esub		a, c, c, @rp0+s0				
				esub		b, d
				esub		b, c
				esub		a, c
				esra		a
				erpn		rp0, #-(96*5)
				eld			@rp0+d0, x1
				eld			@rp0+d0, c
				eld			@rp0+d0, a
				erpd		rp0+d0
				eld			@rp0+d0, b
				erps		rp3+s1
				bnzd		r7, dp2_ch_32_tc_alloc_7
				eld			rp0, rp3				
				brad		dp2_loop_sblimit
				erps		rp3+s0				

;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::;
;::::::::::::::::::::::::[  channel mode 3/1  ]::::::::::::::::::::::;
;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::;
dp2_channel_config_31
/*loop_start*/	eld			rp0, rp3
				ecld		a, r6
				eld			rp1, mc0
				erpn		rp1, a
				eld			a, @rp1						; the number of sbgr.
				eld			rp1, mc1
				erpn		rp1, a
				eld			a, @rp1						; tc_alloc[sbgr]
				ecld		r5, a
; check_tc_alloc
				cmp			eq, r5, #0					; tc_alloc
				brt			dp2_ch_31_tc_alloc_0 
				cmp			eq, r5, #1
				brt			dp2_ch_31_tc_alloc_1	
				cmp			eq, r5, #2
				brt			dp2_ch_31_tc_alloc_2	
				cmp			eq, r5, #3
				brt			dp2_ch_31_tc_alloc_3	
				cmp			eq, r5, #4
				brt			dp2_ch_31_tc_alloc_4 
				cmp			eq, r5, #5
				brt			dp2_ch_31_tc_alloc_5	
.ifdef _DEBUG_
/** debug **/	bra			$
.endif
				
dp2_ch_31_tc_alloc_0
				eld			a, @rp0+s0
				eld			b, @rp0+s0
				eld			c, @rp0+s0
				esub		a, c, d, @rp0+s0 
				eadd		a, d
				esub		b, c
				esub		b, d
				erpn		rp0, #-(96*4)
				eld			@rp0+d0, a
				eld			@rp0+d0, b
				erps		rp3+s1
				bnzd		r7, dp2_ch_31_tc_alloc_0
				eld			rp0, rp3				
				brad		dp2_loop_sblimit
				erps		rp3+s0
dp2_ch_31_tc_alloc_1
				eld			a, @rp0+s0
				eld			b, @rp0+s0
				eld			c, @rp0+s0
				esub		a, c, d, @rp0+s0 
				eadd		a, d
				esub		b, a
				esub		b, d
				erpn		rp0, #-(96*4)
				eld			@rp0+d0, c
				eld			@rp0+d0, b
				eld			@rp0+d0, a
				erps		rp3+s1
				bnzd		r7, dp2_ch_31_tc_alloc_1
				eld			rp0, rp3				
				brad		dp2_loop_sblimit
				erps		rp3+s0
dp2_ch_31_tc_alloc_2
				eld			a, @rp0+s0
				eld			b, @rp0+s0
				eld			c, @rp0+s0
				esub		b, c, d, @rp0+s0 
				esub		b, d
				esub		a, b
				eadd		a, d
				erpn		rp0, #-(96*4)
				eld			@rp0+d0, a
				eld			@rp0+d0, c
				eld			@rp0+d0, b
				erps		rp3+s1
				bnzd		r7, dp2_ch_31_tc_alloc_2
				eld			rp0, rp3				
				brad		dp2_loop_sblimit
				erps		rp3+s0
dp2_ch_31_tc_alloc_3
				eld			a, @rp0+s0
				eld			b, @rp0+s0
				eld			c, @rp0+s0
				eneg		a
				eadd		a, c, d, @rp0+s0 
				eadd		a, d
				esub		b, c
				esub		b, a
				erpn		rp0, #-(96*4)
				eld			@rp0+d0, d
				eld			@rp0+d0, b
				erpd		rp0+d0
				eld			@rp0+d0, a
				erps		rp3+s1
				bnzd		r7, dp2_ch_31_tc_alloc_3
				eld			rp0, rp3				
				brad		dp2_loop_sblimit
				erps		rp3+s0
dp2_ch_31_tc_alloc_4
				eld			a, @rp0+s0
				eld			b, @rp0+s0
				eld			c, @rp0+s0
				esub		b, c, d, @rp0+s0 
				esub		b, d
				esub		a, c
				eadd		a, b
				erpn		rp0, #-(96*4)
				eld			@rp0+d0, a
				eld			@rp0+d0, d
				erpd		rp0+d0
				eld			@rp0+d0, b
				erps		rp3+s1
				bnzd		r7, dp2_ch_31_tc_alloc_4
				eld			rp0, rp3				
				brad		dp2_loop_sblimit
				erps		rp3+s0
dp2_ch_31_tc_alloc_5
				eld			a, @rp0+s0
				eld			b, @rp0+s0
				eld			c, @rp0+s0
				eld			d, @rp0+s0
				eld			x0, a
				eadd		a, b
				esub		a, c
				esub		a, d
				esub		b, x0
				eadd		b, c
				esub		b, d
				esra		a
				esra		b
				erpn		rp0, #-(96*4)
				eld			@rp0+d0, c
				eld			@rp0+d0, d
				eld			@rp0+d0, a
				eld			@rp0+d0, b
				erps		rp3+s1
				bnzd		r7, dp2_ch_31_tc_alloc_5
				eld			rp0, rp3				
				brad		dp2_loop_sblimit
				erps		rp3+s0


;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::;
;:::::::::::::::[  channel mode 3/0 (+2/0) and 2/1  ]::::::::::::::::;
;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::;
dp2_channel_config_30
				jmp			dp0_channel_config_30			; shared routine 



;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::;
;:::::::::::::::::::::::[  channel mode 2/2  ]:::::::::::::::::::::::;
;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::;
dp2_channel_config_22
				jmp			dp0_channel_config_22			; shared routine