library verilog;use verilog.vl_types.all;entity clearable_register is    port(        clk             : in     vl_logic;        din             : in     vl_logic_vector(31 downto 0);        dout            : out    vl_logic_vector(31 downto 0);        clr             : in     vl_logic;        ld              : in     vl_logic    );end clearable_register;