library verilog;use verilog.vl_types.all;entity Super_CPSR is    port(        SC_CTRL_Source  : in     vl_logic_vector(3 downto 0);        SC_CTRL_Type    : in     vl_logic_vector(4 downto 0);        SC_current_CPSR : in     vl_logic_vector(31 downto 0);        SC_alu_result   : in     vl_logic_vector(31 downto 0);        SC_alu_flags    : in     vl_logic_vector(3 downto 0);        SC_shift_flags  : in     vl_logic;        SC_PSR_out      : out    vl_logic_vector(10 downto 0)    );end Super_CPSR;