; Generated by PSoC Designer ???
;
;@Id: boot.tpl#890 @
;=============================================================================
;  FILENAME:   boot.asm
;  VERSION:    4.18
;  DATE:       28 june 2007
;
;  DESCRIPTION:
;  M8C Boot Code for CY8C24x90 microcontroller devices.
;
;  Copyright (C) Cypress Semiconductor 2000-2005. All rights reserved.
;
; NOTES:
; PSoC Designer's Device Editor uses a template file, BOOT.TPL, located in
; the project's root directory to create BOOT.ASM. Any changes made to
; BOOT.ASM will be  overwritten every time the project is generated; therefore
; changes should be made to BOOT.TPL not BOOT.ASM. Care must be taken when
; modifying BOOT.TPL so that replacement strings (such as @PROJECT_NAME)
; are not accidentally modified.
;
;=============================================================================

include ".\lib\GlobalParams.inc"	;File generated by PSoC Designer (Project dependent)
include "m8c.inc"			;Part specific file
include "m8ssc.inc"			;Part specific file
include "memory.inc"			;File generated by PSoC Designer (Project dependent)

;--------------------------------------
; Export Declarations
;--------------------------------------

export __Start
IF	(TOOLCHAIN & HITECH)
ELSE
export __bss_start
export __data_start
export __idata_start
export __func_lit_start
export __text_start
ENDIF
export  _bGetPowerSetting
export   bGetPowerSetting


;--------------------------------------
; Optimization flags
;--------------------------------------
;
; To change the value of these flags, modify the file boot.tpl, not
; boot.asm. See the notes in the banner comment at the beginning of
; this file.

; Optimization for Assembly language (only) projects and C-language projects
; that do not depend on the C compiler to initialize the values of RAM variables.
;   Set to 1: Support for C Run-time Environment initialization
;   Set to 0: Support for C not included. Faster start up, smaller code space.
;
IF	(TOOLCHAIN & HITECH)
; The C compiler will customize the startup code - it's not required here

C_LANGUAGE_SUPPORT:              equ 0
ELSE
C_LANGUAGE_SUPPORT:              equ 1
ENDIF


; For historical reasons, by default the boot code uses an lcall instruction
; to invoke the user's _main code. If _main executes a return instruction,
; boot provides an infinite loop. By changing the following equate from zero
; to 1, boot's lcall will be replaced by a ljmp instruction, saving two
; bytes on the stack which are otherwise required for the return address. If
; this option is enabled, _main must not return. (Beginning with the 4.2
; release, the C compiler automatically places an infinite loop at the end
; of main, rather than a return instruction.)
;
ENABLE_LJMP_TO_MAIN:             equ 0


;-----------------------------------------------------------------------------
; Interrupt Vector Table
;-----------------------------------------------------------------------------
;
; Interrupt vector table entries are 4 bytes long.  Each one contains
; a jump instruction to an ISR (Interrupt Service Routine), although
; very short ISRs could be encoded within the table itself. Normally,
; vector jump targets are modified automatically according to the user
; modules selected. This occurs when the 'Generate Application' opera-
; tion is run causing PSoC Designer to create boot.asm and the other
; configuration files. If you need to hard code a vector, update the
; file boot.tpl, not boot.asm. See the banner comment at the beginning
; of this file.
;-----------------------------------------------------------------------------

    AREA TOP (ROM, ABS, CON)

    org   0                        ;Reset Interrupt Vector
IF	(TOOLCHAIN & HITECH)
;   jmp   __Start                  ;C compiler fills in this vector
ELSE
    jmp   __Start                  ;First instruction executed following a Reset
ENDIF

    org   04h                      ;Supply Monitor Interrupt Vector
    halt                           ;Stop execution if power falls too low

    org   08h                      ;Analog Column 0 Interrupt Vector
    // call	void_handler
    reti

    org   0Ch                      ;Analog Column 1 Interrupt Vector
    // call	void_handler
    reti

    org   18h                      ;VC3 Interrupt Vector
    // call	void_handler
    reti

    org   1Ch                      ;GPIO Interrupt Vector
    ljmp	PSoC_GPIO_ISR
    reti

    org   20h                      ;PSoC Block DBB00 Interrupt Vector
    // call	void_handler
    reti

    org   24h                      ;PSoC Block DBB01 Interrupt Vector
    // call	void_handler
    reti

    org   28h                      ;PSoC Block DCB02 Interrupt Vector
    // call	void_handler
    reti

    org   2Ch                      ;PSoC Block DCB03 Interrupt Vector
    ljmp	_TX8_ISR
    reti

    org   40h                      ;USB Reset Interrupt Vector
    // call	void_handler
    reti

    org   44h                      ;USB SOF Interrupt Vector
    // call	void_handler
    reti

    org   48h                      ;USB EP0 Interrupt Vector
    // call	void_handler
    reti

    org   4Ch                      ;USB EP1 Interrupt Vector
    // call	void_handler
    reti

    org   50h                      ;USB EP2 Interrupt Vector
    // call	void_handler
    reti

    org   54h                      ;USB EP3 Interrupt Vector
    // call	void_handler
    reti

    org   58h                      ;USB EP4 Interrupt Vector
    // call	void_handler
    reti

    org   5Ch                      ;USB Wakeup Interrupt Vector
    // call	void_handler
    reti

    org   60h                      ;PSoC I2C Interrupt Vector
    ljmp	_EzI2Cs_ISR
    reti

    org   64h                      ;Sleep Timer Interrupt Vector
    ljmp	_CYFISNP_SLEEP_ISR
    reti

;-----------------------------------------------------------------------------
;  Start of Execution.
;-----------------------------------------------------------------------------
;  The Supervisory ROM SWBootReset function has already completed the
;  calibrate1 process, loading trim values for 5 volt operation.
;

IF	(TOOLCHAIN & HITECH)
 	AREA PD_startup(CODE, REL, CON)
ELSE
    org 68h
ENDIF
__Start:

    ; initialize values for voltage stabilization, if required,
    ; leaving power-on reset (POR) level at the default (low) level, at
    ; least for now. 
    ;
    M8C_SetBank1
    mov reg[0FAh], 0				;Reset flash location
    mov   reg[VLT_CR], LVD_TBEN_JUST | TRIP_VOLTAGE_JUST
    M8C_SetBank0

    ; %53%20%46%46% Apply Erratum 001-05137 workaround
    mov   A, 20h
    romx
    ; %45%20%46%46% End workaround
	
IF ( WATCHDOG_ENABLE )             ; WDT selected in Global Params
    M8C_EnableWatchDog
ENDIF

    and  reg[CPU_SCR1], ~CPU_SCR1_ECO_ALLOWED  ; Prevent ECO from being enabled

    ;---------------------------
    ; Set up the Temporary stack
    ;---------------------------
    ; A temporary stack is set up for the SSC instructions.
    ; The real stack start will be assigned later.
    ;
_stack_start:          equ 80h
    mov   A, _stack_start          ; Set top of stack to end of used RAM
    swap  SP, A                    ; This is only temporary if going to LMM

    ;------------------------
    ; Set Power-related Trim 
    ;------------------------

IF ( POWER_SETTING & POWER_SET_5V0)            ; *** 5.0 Volt operation   ***

  IF ( AGND_BYPASS )
    ;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
    ; The 5V trim has already been set, but we need to update the AGNDBYP
    ; bit in the write-only BDG_TR register. Recalculate the register
    ; value using the proper trim values.
    ;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
    M8SSC_SetTableVoltageTrim 1, SSCTBL1_TRIM_BGR_5V, AGND_BYPASS_JUST
  ENDIF
ELSE
	; 3.3V operation trim codes
	; Set the IMO and Bandgap trims for 3v operation
    M8SSC_SetTableTrims  1, SSCTBL1_TRIM_IMO_3V_24MHZ, SSCTBL1_TRIM_BGR_3V, AGN_BYPASS_JUST
	
	; Set the IMO Gain Trim for 3v operation
	M8SSC_SetTableIMOGainTrim 2, SSCTBL2_TRIM_IMO_GAIN_3V

ENDIF ; 3.3 Volt Operation

    mov  [bSSC_KEY1],  0           ; Lock out Flash and Supervisiory operations
    mov  [bSSC_KEYSP], 0
				
    ;---------------------------------------
    ; Initialize Crystal Oscillator and PLL
    ;---------------------------------------

    ; Either no ECO, or waiting for stable clock is to be done in main
    M8C_SetBank1
    mov   reg[OSC_CR0], (SLEEP_TIMER_JUST | OSC_CR0_CPU_12MHz)
    M8C_SetBank0
    M8C_ClearWDTAndSleep           ; Reset the watch dog


IF	(TOOLCHAIN & HITECH)
    ;---------------------------------------------
    ; HI-TECH initialization: Enter the Large Memory Model, if applicable
    ;---------------------------------------------
	global		__Lstackps
	mov     a,low __Lstackps
	swap    a,sp

IF ( SYSTEM_LARGE_MEMORY_MODEL )
    RAM_SETPAGE_STK SYSTEM_STACK_PAGE      ; relocate stack page ...
    RAM_SETPAGE_IDX2STK            ; initialize other page pointers
    RAM_SETPAGE_CUR 0
    RAM_SETPAGE_MVW 0
    RAM_SETPAGE_MVR 0
    IF ( SYSTEM_IDXPG_TRACKS_STK_PP ); Now enable paging:
      or    F, FLAG_PGMODE_11b       ; LMM w/ IndexPage<==>StackPage
    ELSE
      or    F, FLAG_PGMODE_10b       ; LMM w/ independent IndexPage
    ENDIF ;  SYSTEM_IDXPG_TRACKS_STK_PP
ENDIF ;  SYSTEM_LARGE_MEMORY_MODEL
ELSE
    ;---------------------------------------------
    ; ImageCraft Enter the Large Memory Model, if applicable
    ;---------------------------------------------
IF ( SYSTEM_LARGE_MEMORY_MODEL )
    RAM_SETPAGE_STK SYSTEM_STACK_PAGE      ; relocate stack page ...
    mov   A, SYSTEM_STACK_BASE_ADDR        ;   and offset, if any
    swap  A, SP
    RAM_SETPAGE_IDX2STK            ; initialize other page pointers
    RAM_SETPAGE_CUR 0
    RAM_SETPAGE_MVW 0
    RAM_SETPAGE_MVR 0

  IF ( SYSTEM_IDXPG_TRACKS_STK_PP ); Now enable paging:
    or    F, FLAG_PGMODE_11b       ; LMM w/ IndexPage<==>StackPage
  ELSE