?? amux8.lst
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HI-TECH Software Macro Assembler (PSoC MCU) V9.61PL1
Fri Oct 03 08:10:14 2008
1 ;;*****************************************************************************
2 ;;*****************************************************************************
3 ;; FILENAME: AMUX8.inc
4 ;; Version: 1.1, Updated on 2008/10/2 at 14:37:16
5 ;; Generated by PSoC Designer ???
6 ;;
7 ;; DESCRIPTION: Assembler declarations for the MUX8 user module interface
8 ;; for the 22/24/25/26/27xxx PSoC family of devices.
9 ;;-----------------------------------------------------------------------------
10 ;; Copyright (c) Cypress MicroSystems 2000-2003. All Rights Reserved.
11 ;;*****************************************************************************
12 ;;*****************************************************************************
13
14 ;--------------------------------------------------
15 ; Constants for AMUX8 API's.
16 ;--------------------------------------------------
17 0000 AMUX8_MUX_COL: equ 0
18 0003 AMUX8_MUX_MASK: equ (03 << (0*2))
19
20 0000 AMUX8_PORT0_0: equ 0h
21 0001 AMUX8_PORT0_1: equ 1h
22 0002 AMUX8_PORT0_2: equ 2h
23 0003 AMUX8_PORT0_3: equ 3h
24 0004 AMUX8_PORT0_4: equ 4h
25 0005 AMUX8_PORT0_5: equ 5h
26 0006 AMUX8_PORT0_6: equ 6h
27 0007 AMUX8_PORT0_7: equ 7h
1 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2 ;;;
3 ;;; M8C.INC -- M8C21030 Microcontroller Device System Declarations
4 ;;;
5 ;;; Copyright (c) 2005 Cypress MicroSystems, Inc. All rights reserved.
6 ;;;
7 ;;;
8 ;;; This file provides address constants, bit field masks and a set of macro
9 ;;; facilities for the Cypress MicroSystems 21x3x Microcontroller devices.
10 ;;;
11 ;;; Last Modified: January 21, 2005
12 ;;;
13 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
14
15 ;;=============================================================================
16 ;; Definition of abbreviations used in the descriptions below
17 ;; (RW) The register or bit supports reads and writes
18 ;; (W) The register or bit is write-only
19 ;; (R) The register or bit is read-only
20 ;; (#) Access to the register is bit specific (see the family datasheet)
21 ;; (RC) The register or bit can be read, but writing a 0 will clear it,
22 ;; writing a 1 will have no effect.
23 ;;=============================================================================
24
25 ;;=============================================================================
26 ;; System Registers
27 ;;=============================================================================
28
29 ;----------------------------
30 ; Flag Register Bit Fields
31 ;----------------------------
32 00C0 FLAG_PGMODE_MASK: equ 0C0h ; Paging control for > 256 bytes of RAM
33 0000 FLAG_PGMODE_0: equ 00h ; Direct to Page 0, indexed to Page 0
34 0040 FLAG_PGMODE_1: equ 40h ; Direct to Page 0, indexed to STK_PP page
35 0080 FLAG_PGMODE_2: equ 80h ; Direct to CUR_PP page, indexed to IDX_PP page
36 00C0 FLAG_PGMODE_3: equ 0C0h ; Direct to CUR_PP page, indexed to STK_PP page
37 0000 FLAG_PGMODE_00b: equ 00h ; Same as PGMODE_0
38 0040 FLAG_PGMODE_01b: equ 40h ; Same as PGMODE_1
39 0080 FLAG_PGMODE_10b: equ 80h ; Same as PGMODE_2
40 00C0 FLAG_PGMODE_11b: equ 0C0h ; Same as PGMODE_3
41 0010 FLAG_XIO_MASK: equ 10h ; I/O Bank select for register space
42 0008 FLAG_SUPER: equ 08h ; Supervisor Mode
43 0004 FLAG_CARRY: equ 04h ; Carry Condition Flag
44 0002 FLAG_ZERO: equ 02h ; Zero Condition Flag
45 0001 FLAG_GLOBAL_IE: equ 01h ; Glogal Interrupt Enable
46
47
48 ;;=============================================================================
49 ;; Register Space, Bank 0
50 ;;=============================================================================
51
52 ;------------------------------------------------
53 ; Port Registers
54 ; Note: Also see this address range in Bank 1.
55 ;------------------------------------------------
56 ; Port 0
57 0000 PRT0DR: equ 00h ; Port 0 Data Register (RW)
58 0001 PRT0IE: equ 01h ; Port 0 Interrupt Enable Register (RW)
59 0002 PRT0GS: equ 02h ; Port 0 Global Select Register (RW)
60 0003 PRT0DM2: equ 03h ; Port 0 Drive Mode 2 (RW)
61 ; Port 1
62 0004 PRT1DR: equ 04h ; Port 1 Data Register (RW)
63 0005 PRT1IE: equ 05h ; Port 1 Interrupt Enable Register (RW)
64 0006 PRT1GS: equ 06h ; Port 1 Global Select Register (RW)
65 0007 PRT1DM2: equ 07h ; Port 1 Drive Mode 2 (RW)
66 ; Port 2
67 0008 PRT2DR: equ 08h ; Port 2 Data Register (RW)
68 0009 PRT2IE: equ 09h ; Port 2 Interrupt Enable Register (RW)
69 000A PRT2GS: equ 0Ah ; Port 2 Global Select Register (RW)
70 000B PRT2DM2: equ 0Bh ; Port 2 Drive Mode 2 (RW)
71 ; Port 3
72 000C PRT3DR: equ 0Ch ; Port 3 Data Register (RW)
73 000D PRT3IE: equ 0Dh ; Port 3 Interrupt Enable Register (RW)
74 000E PRT3GS: equ 0Eh ; Port 3 Global Select Register (RW)
75 000F PRT3DM2: equ 0Fh ; Port 3 Drive Mode 2 (RW)
76
77 ;------------------------------------------------
78 ; Digital PSoC(tm) block Registers
79 ; Note: Also see this address range in Bank 1.
80 ;------------------------------------------------
81 ; Digital PSoC block 00, Basic Type B
82 0020 DBB00DR0: equ 20h ; data register 0 (#)
83 0021 DBB00DR1: equ 21h ; data register 1 (W)
84 0022 DBB00DR2: equ 22h ; data register 2 (RW)
85 0023 DBB00CR0: equ 23h ; control & status register 0 (#)
86
87 ; Digital PSoC block 01, Basic Type B
88 0024 DBB01DR0: equ 24h ; data register 0 (#)
89 0025 DBB01DR1: equ 25h ; data register 1 (W)
90 0026 DBB01DR2: equ 26h ; data register 2 (RW)
91 0027 DBB01CR0: equ 27h ; control & status register 0 (#)
92
93 ; Digital PSoC block 02, Communications Type B
94 0028 DCB02DR0: equ 28h ; data register 0 (#)
95 0029 DCB02DR1: equ 29h ; data register 1 (W)
96 002A DCB02DR2: equ 2Ah ; data register 2 (RW)
97 002B DCB02CR0: equ 2Bh ; control & status register 0 (#)
98
99 ; Digital PSoC block 03, Communications Type B
100 002C DCB03DR0: equ 2Ch ; data register 0 (#)
101 002D DCB03DR1: equ 2Dh ; data register 1 (W)
102 002E DCB03DR2: equ 2Eh ; data register 2 (RW)
103 002F DCB03CR0: equ 2Fh ; control & status register 0 (#)
104
105 ;-------------------------------------
106 ; Analog Control Registers
107 ;-------------------------------------
108 0060 AMX_IN: equ 60h ; Analog Input Multiplexor Control (RW)
109 000C AMX_IN_ACI1: equ 0Ch ; MASK: column 1 input mux
110 0003 AMX_IN_ACI0: equ 03h ; MASK: column 0 input mux
111
112 0061 AMUXCFG: equ 61h ; Analog MUX Configuration
113 0030 AMUXCFG_INTCAP: equ 30h ;
114 000E AMUXCFG_MUXCLK: equ 0Eh ;
115 0001 AMUXCFG_EN: equ 01h ;
116
117 0062 PWM_CR: equ 62h ; Pulse-Width Modulator Control
118 0038 PWM_CR_HIGH: equ 38h ; MASK: PWM high time
119 0006 PWM_CR_LOW: equ 06h ; MASK: PWM low time
120 0001 PWM_CR_EN: equ 01h ; MASK: Enable/Disable PWM function
121
122 0064 CMP_CR0: equ 64h ; Analog Comparator Bus Register (#)
123 0020 CMP_CR0_COMP1: equ 20h ; MASK: Column 1 comparator state (R)
124 0010 CMP_CR0_COMP0: equ 10h ; MASK: Column 0 comparator state (R)
125 0002 CMP_CR0_AINT1: equ 02h ; MASK: Column 1 interrupt source (RW)
126 0001 CMP_CR0_AINT0: equ 01h ; MASK: Column 0 interrupt source (RW)
127
128 0066 CMP_CR1: equ 66h ; Analog Comparator Bus 1 Register (RW)
129 0020 CMP_CR1_CLDIS1: equ 20h ; MASK: Column 1 comparator output latch
130 0010 CMP_CR1_CLDIS0: equ 10h ; MASK: Column 0 comparator output latch
131
132 0068 ADC0_CR: equ 68h ; Analog Column 0 Configuration
133 0080 ADC0_CR_CMPST: equ 80h ;
134 0040 ADC0_CR_LOREN: equ 40h ;
135 0020 ADC0_CR_SHEN: equ 20h ;
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