?? adc10int.lst
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164 ;-----------------------------------------------
165 006C TMP_DR0: equ 6Ch ; Temporary Data Register 0 (RW)
166 006D TMP_DR1: equ 6Dh ; Temporary Data Register 1 (RW)
167 006E TMP_DR2: equ 6Eh ; Temporary Data Register 2 (RW)
168 006F TMP_DR3: equ 6Fh ; Temporary Data Register 3 (RW)
169
170 ;------------------------------------------------
171 ; Row Digital Interconnects
172 ;
173 ; Note: the following registers are mapped into
174 ; both register bank 0 AND register bank 1.
175 ;------------------------------------------------
176
177 00B0 RDI0RI: equ 0B0h ; Row Digital Interconnect Row 0 Input Reg (RW)
178 00B1 RDI0SYN: equ 0B1h ; Row Digital Interconnect Row 0 Sync Reg (RW)
179 00B2 RDI0IS: equ 0B2h ; Row 0 Input Select Register (RW)
180 00B3 RDI0LT0: equ 0B3h ; Row 0 Look Up Table Register 0 (RW)
181 00B4 RDI0LT1: equ 0B4h ; Row 0 Look Up Table Register 1 (RW)
182 00B5 RDI0RO0: equ 0B5h ; Row 0 Output Register 0 (RW)
183 00B6 RDI0RO1: equ 0B6h ; Row 0 Output Register 1 (RW)
184
185 ;-----------------------------------------------
186 ; Ram Page Pointers
187 ;-----------------------------------------------
188 00D0 CUR_PP: equ 0D0h ; Current Page Pointer
189 00D1 STK_PP: equ 0D1h ; Stack Page Pointer
190 00D3 IDX_PP: equ 0D3h ; Index Page Pointer
191 00D4 MVR_PP: equ 0D4h ; MVI Read Page Pointer
192 00D5 MVW_PP: equ 0D5h ; MVI Write Page Pointer
193
194 ;------------------------------------------------
195 ; I2C Configuration Registers
196 ;------------------------------------------------
197 00D6 I2C_CFG: equ 0D6h ; I2C Configuration Register (RW)
198 0040 I2C_CFG_PINSEL: equ 40h ; MASK: Select P1[0] and P1[1] for I2C
199 0020 I2C_CFG_BUSERR_IE: equ 20h ; MASK: Enable interrupt on Bus Error
200 0010 I2C_CFG_STOP_IE: equ 10h ; MASK: Enable interrupt on Stop
201 0000 I2C_CFG_CLK_RATE_100K: equ 00h ; MASK: I2C clock set at 100K
202 0004 I2C_CFG_CLK_RATE_400K: equ 04h ; MASK: I2C clock set at 400K
203 0008 I2C_CFG_CLK_RATE_50K: equ 08h ; MASK: I2C clock set at 50K
204 000C I2C_CFG_CLK_RATE: equ 0Ch ; MASK: I2C clock rate setting mask
205 0002 I2C_CFG_PSELECT_MASTER: equ 02h ; MASK: Enable I2C Master
206 0001 I2C_CFG_PSELECT_SLAVE: equ 01h ; MASK: Enable I2C Slave
207
208 00D7 I2C_SCR: equ 0D7h ; I2C Status and Control Register (#)
209 0080 I2C_SCR_BUSERR: equ 80h ; MASK: I2C Bus Error detected (RC)
210 0040 I2C_SCR_LOSTARB: equ 40h ; MASK: I2C Arbitration lost (RC)
211 0020 I2C_SCR_STOP: equ 20h ; MASK: I2C Stop detected (RC)
212 0010 I2C_SCR_ACK: equ 10h ; MASK: ACK the last byte (RW)
213 0008 I2C_SCR_ADDR: equ 08h ; MASK: Address rcv'd is Slave address (RC)
214 0004 I2C_SCR_XMIT: equ 04h ; MASK: Set transfer to tranmit mode (RW)
215 0002 I2C_SCR_LRB: equ 02h ; MASK: Last recieved bit (RC)
216 0001 I2C_SCR_BYTECOMPLETE: equ 01h ; MASK: Transfer of byte complete (RC)
217
218 00D8 I2C_DR: equ 0D8h ; I2C Data Register (RW)
219
220 00D9 I2C_MSCR: equ 0D9h ; I2C Master Status and Control Register (#)
221 0008 I2C_MSCR_BUSY: equ 08h ; MASK: I2C Busy (Start detected) (R)
222 0004 I2C_MSCR_MODE: equ 04h ; MASK: Start has been generated (R)
223 0002 I2C_MSCR_RESTART: equ 02h ; MASK: Generate a Restart condition (RW)
224+ 0001 I2C_MSCR_START: equ 01h ; MASK: Generate a Start condition (RW)
225
226 ;------------------------------------------------
227 ; System and Global Resource Registers
228 ;------------------------------------------------
229 00DA INT_CLR0: equ 0DAh ; Interrupt Clear Register 0 (RW)
230 ; Use INT_MSK0 bit field masks
231 00DB INT_CLR1: equ 0DBh ; Interrupt Clear Register 1 (RW)
232 ; Use INT_MSK1 bit field masks
233 00DD INT_CLR3: equ 0DDh ; Interrupt Clear Register 3 (RW)
234 ; Use INT_MSK3 bit field masks
235
236 00DE INT_MSK3: equ 0DEh ; I2C and Software Mask Register (RW)
237 0080 INT_MSK3_ENSWINT: equ 80h ; MASK: enable/disable SW interrupt
238 0001 INT_MSK3_I2C: equ 01h ; MASK: enable/disable I2C interrupt
239
240 00E0 INT_MSK0: equ 0E0h ; General Interrupt Mask Register (RW)
241 0080 INT_MSK0_VC3: equ 80h ; MASK: enable/disable VC3 interrupt
242 0040 INT_MSK0_SLEEP: equ 40h ; MASK: enable/disable sleep interrupt
243 0020 INT_MSK0_GPIO: equ 20h ; MASK: enable/disable GPIO interrupt
244 0004 INT_MSK0_ACOLUMN_1: equ 04h ; MASK: enable/disable Analog col 1 interrupt
245 0002 INT_MSK0_ACOLUMN_0: equ 02h ; MASK: enable/disable Analog col 0 interrupt
246 0001 INT_MSK0_VOLTAGE_MONITOR: equ 01h ; MASK: enable/disable Volts interrupt
247
248 00E1 INT_MSK1: equ 0E1h ; Digital PSoC block Mask Register (RW)
249 0008 INT_MSK1_DCB03: equ 08h ; MASK: enable/disable DCB03 block interrupt
250 0004 INT_MSK1_DCB02: equ 04h ; MASK: enable/disable DCB02 block interrupt
251 0002 INT_MSK1_DBB01: equ 02h ; MASK: enable/disable DBB01 block interrupt
252 0001 INT_MSK1_DBB00: equ 01h ; MASK: enable/disable DBB00 block interrupt
253
254 00E2 INT_VC: equ 0E2h ; Interrupt vector register (RC)
255 00E3 RES_WDT: equ 0E3h ; Watch Dog Timer Register (W)
256
257 ; DECIMATOR Control Registers
258 00E6 DEC_CR0: equ 0E6h ; Data Control Register 0 (RW)
259 00E7 DEC_CR1: equ 0E7h ; Data Control Register 1 (RW)
260
261 ;------------------------------------------------------
262 ; System Status and Control Registers
263 ;
264 ; Note: The following registers are mapped into both
265 ; register bank 0 AND register bank 1.
266 ;------------------------------------------------------
267 00F7 CPU_F: equ 0F7h ; CPU Flag Register Access (RO)
268 ; Use FLAG_ masks defined at top of file
269
270 00FD DAC_D: equ 0FDh ; DAC Data Register (RW)
271
272 00FE CPU_SCR1: equ 0FEh ; CPU Status and Control Register #1 (#)
273 0080 CPU_SCR1_IRESS: equ 80h ; MASK: flag, Internal Reset Status bit
274 0010 CPU_SCR1_SLIMO: equ 10h ; MASK: Slow IMO (internal main osc) enable
275 0008 CPU_SCR1_ECO_ALWD_WR: equ 08h ; MASK: flag, ECO allowed has been written
276 0004 CPU_SCR1_ECO_ALLOWED: equ 04h ; MASK: ECO allowed to be enabled
277 0001 CPU_SCR1_IRAMDIS: equ 01h ; MASK: Disable RAM initialization on WDR
278
279 00FF CPU_SCR0: equ 0FFh ; CPU Status and Control Register #2 (#)
280 0080 CPU_SCR0_GIE_MASK: equ 80h ; MASK: Global Interrupt Enable shadow
281 0020 CPU_SCR0_WDRS_MASK: equ 20h ; MASK: Watch Dog Timer Reset
282 0010 CPU_SCR0_PORS_MASK: equ 10h ; MASK: power-on reset bit PORS
283 0008 CPU_SCR0_SLEEP_MASK: equ 08h ; MASK: Enable Sleep
284 0001 CPU_SCR0_STOP_MASK: equ 01h ; MASK: Halt CPU bit
285
286
287 ;;=============================================================================
288 ;; Register Space, Bank 1
289 ;;=============================================================================
290
291 ;------------------------------------------------
292 ; Port Registers
293 ; Note: Also see this address range in Bank 0.
294 ;------------------------------------------------
295 ; Port 0
296 0000 PRT0DM0: equ 00h ; Port 0 Drive Mode 0 (RW)
297 0001 PRT0DM1: equ 01h ; Port 0 Drive Mode 1 (RW)
298 0002 PRT0IC0: equ 02h ; Port 0 Interrupt Control 0 (RW)
299 0003 PRT0IC1: equ 03h ; Port 0 Interrupt Control 1 (RW)
300
301 ; Port 1
302 0004 PRT1DM0: equ 04h ; Port 1 Drive Mode 0 (RW)
303 0005 PRT1DM1: equ 05h ; Port 1 Drive Mode 1 (RW)
304 0006 PRT1IC0: equ 06h ; Port 1 Interrupt Control 0 (RW)
305 0007 PRT1IC1: equ 07h ; Port 1 Interrupt Control 1 (RW)
306
307 ; Port 2
308 0008 PRT2DM0: equ 08h ; Port 2 Drive Mode 0 (RW)
309 0009 PRT2DM1: equ 09h ; Port 2 Drive Mode 1 (RW)
310 000A PRT2IC0: equ 0Ah ; Port 2 Interrupt Control 0 (RW)
311 000B PRT2IC1: equ 0Bh ; Port 2 Interrupt Control 1 (RW)
312
313 ; Port 3
314 000C PRT3DM0: equ 0Ch ; Port 3 Drive Mode 0 (RW)
315 000D PRT3DM1: equ 0Dh ; Port 3 Drive Mode 1 (RW)
316 000E PRT3IC0: equ 0Eh ; Port 3 Interrupt Control 0 (RW)
317 000F PRT3IC1: equ 0Fh ; Port 3 Interrupt Control 1 (RW)
318
319 ;------------------------------------------------
320 ; Digital PSoC(tm) block Registers
321 ; Note: Also see this address range in Bank 0.
322 ;------------------------------------------------
323
324 ; Digital PSoC block 00, Basic Type B
325 0020 DBB00FN: equ 20h ; Function Register (RW)
326 0021 DBB00IN: equ 21h ; Input Register (RW)
327 0022 DBB00OU: equ 22h ; Output Register (RW)
328
329 ; Digital PSoC block 01, Basic Type B
330 0024 DBB01FN: equ 24h ; Function Register (RW)
331 0025 DBB01IN: equ 25h ; Input Register (RW)
332 0026 DBB01OU: equ 26h ; Output Register (RW)
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