?? ezi2cs.lst
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502 or F, FLAG_GLOBAL_IE
503 1C5C endm
504
505 macro M8C_DisableGInt
506 and F, ~FLAG_GLOBAL_IE
507 1C5C endm
508
509 ;----------------------------------------------------
510 ; Enable/Disable Interrupt Mask
511 ;
512 ; Use the following macros to enable/disable
513 ; bits in the Interrupt mask registers,
514 ; INT_MSK0, INT_MSK1 or INT_MSK3.
515 ;
516 ; Usage: M8C_DisableIntMask INT_MSKN, MASK
517 ; M8C_EnableIntMask INT_MSKN, MASK
518 ;
519 ; where INT_MSKN is INT_MSK0, INT_MSK1 or INT_MSK3
520 ; and MASK is the bit set to enable or disable
521 ;----------------------------------------------------
522 ; Disable Interrupt Bit Mask(s)
523 macro M8C_DisableIntMask
524 and reg[@0], ~@1 ; disable specified interrupt enable bit
525 1C5C endm
526
527 ; Enable Interrupt Bit Mask(s)
528 macro M8C_EnableIntMask
529 or reg[@0], @1 ; enable specified interrupt enable bit
530 1C5C endm
531
532 ;----------------------------------------------------
533 ; Clear Posted Interrupt Flag Mask
534 ;
535 ; Use the following macros to clear the
536 ; bits in the Interrupt Clear registers,
537 ; INT_CLR0, INT_CLR1 or INT_CLR3.
538 ; Usage: M8C_ClearIntFlag INT_CLRN, MASK
539 ;
540 ; where INT_MSKN is INT_CLR0, INT_CLR1 or INT_CLR3
541 ; and MASK is the bit set to enable or disable
542 ;----------------------------------------------------
543 macro M8C_ClearIntFlag
544 mov reg[@0], ~@1 ; clear specified interrupt enable bit
545 1C5C endm
546
547 ;----------------------------------------------------
548 ; Power-On Reset & WatchDog Timer Functions
549 ;----------------------------------------------------
550 macro M8C_EnableWatchDog
551 and reg[CPU_SCR0], ~CPU_SCR0_PORS_MASK
552 1C5C endm
553
554 macro M8C_ClearWDT
555 mov reg[RES_WDT], 00h
556 1C5C endm
557
558 macro M8C_ClearWDTAndSleep
559 mov reg[RES_WDT], 38h
560 1C5C endm
561
562 ;----------------------------------------------------
563 ; Sleep, CPU Stop & Software Reset
564 ;----------------------------------------------------
565 macro M8C_Sleep
566 or reg[CPU_SCR0], CPU_SCR0_SLEEP_MASK
567 ; The next instruction to be executed depends on the state of the
568 ; various interrupt enable bits. If some interrupts are enabled
569 ; and the global interrupts are disabled, the next instruction will
570 ; be the one that follows the invocation of this macro. If global
571 ; interrupts are also enabled then the next instruction will be
572 ; from the interrupt vector table. If no interrupts are enabled
573 ; then the CPU sleeps forever.
574 1C5C endm
575
576 macro M8C_Stop
577 ; In general, you probably don't want to do this, but here's how:
578 or reg[CPU_SCR0], CPU_SCR0_STOP_MASK
579 ; Next instruction to be executed is located in the interrupt
580 ; vector table entry for Power-On Reset.
581 1C5C endm
582
583 macro M8C_Reset
584 ; Restore CPU to the power-on reset state.
585 mov A, 0
586 SSC
587 ; Next non-supervisor instruction will be at interrupt vector 0.
588 1C5C endm
589
590 ;----------------------------------------------------
591 ; ImageCraft Code Compressor Actions
592 ;----------------------------------------------------
593 ; Suspend Code Compressor
594 ; Must not span a RET or RETI instruction
595 ; without resuming code compression
596 macro Suspend_CodeCompressor
597 or F, 0
598 1C5C endm
599
600 ; Resume Code Compression
601 macro Resume_CodeCompressor
602 add SP, 0
603 1C5C endm
1 ;;*****************************************************************************
2 ;;*****************************************************************************
3 ;;
4 ;; FILENAME: Memory.inc
5 ;;
6 ;; DESCRIPTION: Memory Model and Stack Parameter Definitions for
7 ;; 21x3x PSoC devices.
8 ;;
9 ;; LAST MODIFIED: August 17, 2004
10 ;;
11 ;;-----------------------------------------------------------------------------
12 ;; Copyright (c) Cypress MicroSystems 2004. All Rights Reserved.
13 ;;*****************************************************************************
14 ;;*****************************************************************************
15 ;
16 ;
17 ; ******** Define Memory Model and Stack parameters ********
18 ;
19 0001 IMAGECRAFT: equ 1
20 0002 HITECH: equ 2
21 0002 TOOLCHAIN: equ HITECH
22 0001 SYSTEM_LARGE_MEMORY_MODEL: equ 1
23 0000 SYSTEM_SMALL_MEMORY_MODEL: equ 0
24 0001 SYSTEM_STACK_PAGE: equ 1
25 0000 SYSTEM_STACK_PAGE_OFFSET: equ 0
26 0002 SYSTEM_TOOLS: equ 2
27 0000 SYSTEM_IDXPG_TRACKS_STK_PP: equ 0
28 0001 SYSTEM_IDXPG_TRACKS_IDX_PP: equ 1
29 0000 SYSTEM_MULTIPAGE_STACK: equ 0
30
31
32 ; ******* Function Class Definitions *******
33 ;
34 ; These definitions are used to describe RAM access patterns. They provide
35 ; documentation and they control prologue and epilogue macros that perform
36 ; the necessary housekeeping functions for large memory model devices like
37 ; the CY8C27x66 and CY8C29x66.
38
39 0001 RAM_USE_CLASS_1: equ 1 ; PUSH, POP & I/O access
40 0002 RAM_USE_CLASS_2: equ 2 ; Indexed address mode on stack page
41 0004 RAM_USE_CLASS_3: equ 4 ; Indexed address mode to any page
42 0008 RAM_USE_CLASS_4: equ 8 ; Direct/Indirect address mode access
43
44
45 ; ******* Page Pointer Manipulation Macros *******
46 ;
47 ; Most of the following macros are conditionally compiled so they only
48 ; produce code if the large memory model is selected.
49
50 ;-----------------------------------------------
51 ; Set Stack Page Macro
52 ;-----------------------------------------------
53 ;
54 ; DESC: Modify STK_PP in the large or small memory Models.
55 ;
56 ; INPUT: Constant (e.g., SYSTEM_STACK_PAGE) that specifies the RAM page on
57 ; which stack operations like PUSH and POP store and retrieve their
58 ; data
59 ;
60 ; COST: 8 instruction cycles (in LMM only)
61
62 macro RAM_SETPAGE_STK( PG_NUMBER )
63 IF ( SYSTEM_LARGE_MEMORY_MODEL )
64 mov reg[STK_PP], @PG_NUMBER
65 ENDIF
66 1C5C endm
67
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