; Generated by PSoC Designer ???
;
; EzI2CsSDA address and mask equates
EzI2CsSDA_Data_ADDR:	equ	4h
EzI2CsSDA_DriveMode_0_ADDR:	equ	104h
EzI2CsSDA_DriveMode_1_ADDR:	equ	105h
EzI2CsSDA_DriveMode_2_ADDR:	equ	7h
EzI2CsSDA_GlobalSelect_ADDR:	equ	6h
EzI2CsSDA_IntCtrl_0_ADDR:	equ	106h
EzI2CsSDA_IntCtrl_1_ADDR:	equ	107h
EzI2CsSDA_IntEn_ADDR:	equ	5h
EzI2CsSDA_MASK:	equ	20h
EzI2CsSDA_MUXBusCtrl_ADDR:	equ	1d9h
; EzI2CsSDA_Data access macros
;   GetEzI2CsSDA_Data macro, return in a
macro GetEzI2CsSDA_Data
	mov		a,[Port_1_Data_SHADE]
	and		a, 20h
endm
;   SetEzI2CsSDA_Data macro
macro SetEzI2CsSDA_Data
	or		[Port_1_Data_SHADE], 20h
	mov		a, [Port_1_Data_SHADE]
	mov		reg[EzI2CsSDA_Data_ADDR], a
endm
;   ClearEzI2CsSDA_Data macro
macro ClearEzI2CsSDA_Data
	and		[Port_1_Data_SHADE], ~20h
	mov		a, [Port_1_Data_SHADE]
	mov		reg[EzI2CsSDA_Data_ADDR], a
endm

; EzI2CsSCL address and mask equates
EzI2CsSCL_Data_ADDR:	equ	4h
EzI2CsSCL_DriveMode_0_ADDR:	equ	104h
EzI2CsSCL_DriveMode_1_ADDR:	equ	105h
EzI2CsSCL_DriveMode_2_ADDR:	equ	7h
EzI2CsSCL_GlobalSelect_ADDR:	equ	6h
EzI2CsSCL_IntCtrl_0_ADDR:	equ	106h
EzI2CsSCL_IntCtrl_1_ADDR:	equ	107h
EzI2CsSCL_IntEn_ADDR:	equ	5h
EzI2CsSCL_MASK:	equ	80h
EzI2CsSCL_MUXBusCtrl_ADDR:	equ	1d9h
; EzI2CsSCL_Data access macros
;   GetEzI2CsSCL_Data macro, return in a
macro GetEzI2CsSCL_Data
	mov		a,[Port_1_Data_SHADE]
	and		a, 80h
endm
;   SetEzI2CsSCL_Data macro
macro SetEzI2CsSCL_Data
	or		[Port_1_Data_SHADE], 80h
	mov		a, [Port_1_Data_SHADE]
	mov		reg[EzI2CsSCL_Data_ADDR], a
endm
;   ClearEzI2CsSCL_Data macro
macro ClearEzI2CsSCL_Data
	and		[Port_1_Data_SHADE], ~80h
	mov		a, [Port_1_Data_SHADE]
	mov		reg[EzI2CsSCL_Data_ADDR], a
endm