{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/serial.vhd" 21 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clkbaud8x " "Info: Detected ripple clock \"clkbaud8x\" as buffer" {  } { { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/serial.vhd" 42 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clkbaud8x" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register key_entry2 register key_entry1 150.78 MHz 6.632 ns Internal " "Info: Clock \"clk\" has Internal fmax of 150.78 MHz between source register \"key_entry2\" and destination register \"key_entry1\" (period= 6.632 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.924 ns + Longest register register " "Info: + Longest register to register delay is 1.924 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns key_entry2 1 REG LC_X10_Y10_N6 18 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y10_N6; Fanout = 18; REG Node = 'key_entry2'" {  } { { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/" "" "" { key_entry2 } "NODE_NAME" } "" } } { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/serial.vhd" 55 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.812 ns) + CELL(1.112 ns) 1.924 ns key_entry1 2 REG LC_X11_Y10_N5 4 " "Info: 2: + IC(0.812 ns) + CELL(1.112 ns) = 1.924 ns; Loc. = LC_X11_Y10_N5; Fanout = 4; REG Node = 'key_entry1'" {  } { { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/" "" "1.924 ns" { key_entry2 key_entry1 } "NODE_NAME" } "" } } { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/serial.vhd" 54 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.112 ns 57.80 % " "Info: Total cell delay = 1.112 ns ( 57.80 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.812 ns 42.20 % " "Info: Total interconnect delay = 0.812 ns ( 42.20 % )" {  } {  } 0}  } { { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/" "" "1.924 ns" { key_entry2 key_entry1 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.924 ns" { key_entry2 key_entry1 } { 0.000ns 0.812ns } { 0.000ns 1.112ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-4.447 ns - Smallest " "Info: - Smallest clock skew is -4.447 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.925 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.925 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_152 39 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 39; CLK Node = 'clk'" {  } { { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/" "" "" { clk } "NODE_NAME" } "" } } { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/serial.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.711 ns) 2.925 ns key_entry1 2 REG LC_X11_Y10_N5 4 " "Info: 2: + IC(0.745 ns) + CELL(0.711 ns) = 2.925 ns; Loc. = LC_X11_Y10_N5; Fanout = 4; REG Node = 'key_entry1'" {  } { { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/" "" "1.456 ns" { clk key_entry1 } "NODE_NAME" } "" } } { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/serial.vhd" 54 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 74.53 % " "Info: Total cell delay = 2.180 ns ( 74.53 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.745 ns 25.47 % " "Info: Total interconnect delay = 0.745 ns ( 25.47 % )" {  } {  } 0}  } { { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/" "" "2.925 ns" { clk key_entry1 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.925 ns" { clk clk~out0 key_entry1 } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.372 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 7.372 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_152 39 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 39; CLK Node = 'clk'" {  } { { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/" "" "" { clk } "NODE_NAME" } "" } } { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/serial.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns clkbaud8x 2 REG LC_X8_Y10_N0 40 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N0; Fanout = 40; REG Node = 'clkbaud8x'" {  } { { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/" "" "1.680 ns" { clk clkbaud8x } "NODE_NAME" } "" } } { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/serial.vhd" 42 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.512 ns) + CELL(0.711 ns) 7.372 ns key_entry2 3 REG LC_X10_Y10_N6 18 " "Info: 3: + IC(3.512 ns) + CELL(0.711 ns) = 7.372 ns; Loc. = LC_X10_Y10_N6; Fanout = 18; REG Node = 'key_entry2'" {  } { { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/" "" "4.223 ns" { clkbaud8x key_entry2 } "NODE_NAME" } "" } } { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/serial.vhd" 55 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns 42.25 % " "Info: Total cell delay = 3.115 ns ( 42.25 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.257 ns 57.75 % " "Info: Total interconnect delay = 4.257 ns ( 57.75 % )" {  } {  } 0}  } { { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/" "" "7.372 ns" { clk clkbaud8x key_entry2 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.372 ns" { clk clk~out0 clkbaud8x key_entry2 } { 0.000ns 0.000ns 0.745ns 3.512ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0}  } { { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/" "" "2.925 ns" { clk key_entry1 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.925 ns" { clk clk~out0 key_entry1 } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } } } { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/" "" "7.372 ns" { clk clkbaud8x key_entry2 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.372 ns" { clk clk~out0 clkbaud8x key_entry2 } { 0.000ns 0.000ns 0.745ns 3.512ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/serial.vhd" 55 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/serial.vhd" 54 -1 0 } }  } 0}  } { { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/" "" "1.924 ns" { key_entry2 key_entry1 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.924 ns" { key_entry2 key_entry1 } { 0.000ns 0.812ns } { 0.000ns 1.112ns } } } { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/" "" "2.925 ns" { clk key_entry1 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.925 ns" { clk clk~out0 key_entry1 } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } } } { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/" "" "7.372 ns" { clk clkbaud8x key_entry2 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.372 ns" { clk clk~out0 clkbaud8x key_entry2 } { 0.000ns 0.000ns 0.745ns 3.512ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0}