{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Feb 07 21:58:05 2008 " "Info: Processing started: Thu Feb 07 21:58:05 2008" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off serial -c serial " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off serial -c serial" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "serial EP1C6Q240C8 " "Info: Selected device EP1C6Q240C8 for design \"serial\"" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Info: Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C12Q240C8 " "Info: Device EP1C12Q240C8 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1000 MHz " "Info: Assuming a global fmax requirement of 1000 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources." {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk Global clock in PIN 152 " "Info: Automatically promoted signal \"clk\" to use Global clock in PIN 152" {  } { { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/serial.vhd" 21 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "clkbaud8x Global clock " "Info: Automatically promoted some destinations of signal \"clkbaud8x\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "clkbaud8x " "Info: Destination \"clkbaud8x\" may be non-global or may not use global clock" {  } { { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/serial.vhd" 42 -1 0 } }  } 0}  } { { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/serial.vhd" 42 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "rst Global clock " "Info: Automatically promoted signal \"rst\" to use Global clock" {  } { { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/serial.vhd" 22 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "rst " "Info: Pin \"rst\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/serial.vhd" 22 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "rst" } } } } { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/" "" "" { rst } "NODE_NAME" } "" } } { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/serial.fld" "" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/serial.fld" "" "" { rst } "NODE_NAME" } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}