{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "1.850 ns register register " "Info: Estimated most critical path is register to register delay of 1.850 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns key_entry2 1 REG LAB_X10_Y10 18 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X10_Y10; Fanout = 18; REG Node = 'key_entry2'" {  } { { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/" "" "" { key_entry2 } "NODE_NAME" } "" } } { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/serial.vhd" 55 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.738 ns) + CELL(1.112 ns) 1.850 ns key_entry1 2 REG LAB_X11_Y10 4 " "Info: 2: + IC(0.738 ns) + CELL(1.112 ns) = 1.850 ns; Loc. = LAB_X11_Y10; Fanout = 4; REG Node = 'key_entry1'" {  } { { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/" "" "1.850 ns" { key_entry2 key_entry1 } "NODE_NAME" } "" } } { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/serial.vhd" 54 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.112 ns 60.11 % " "Info: Total cell delay = 1.112 ns ( 60.11 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.738 ns 39.89 % " "Info: Total interconnect delay = 0.738 ns ( 39.89 % )" {  } {  } 0}  } { { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/" "" "1.850 ns" { key_entry2 key_entry1 } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Info: Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 1 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 1%." {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Warning" "WFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "10 " "Warning: The following 10 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "en\[0\] GND " "Info: Pin en\[0\] has GND driving its datain port" {  } { { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/serial.vhd" 25 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "en\[0\]" } } } } { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/" "" "" { en[0] } "NODE_NAME" } "" } } { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/serial.fld" "" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/serial.fld" "" "" { en[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "en\[1\] GND " "Info: Pin en\[1\] has GND driving its datain port" {  } { { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/serial.vhd" 25 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "en\[1\]" } } } } { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/" "" "" { en[1] } "NODE_NAME" } "" } } { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/serial.fld" "" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/serial.fld" "" "" { en[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "en\[2\] GND " "Info: Pin en\[2\] has GND driving its datain port" {  } { { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/serial.vhd" 25 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "en\[2\]" } } } } { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/" "" "" { en[2] } "NODE_NAME" } "" } } { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/serial.fld" "" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/serial.fld" "" "" { en[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "en\[3\] GND " "Info: Pin en\[3\] has GND driving its datain port" {  } { { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/serial.vhd" 25 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "en\[3\]" } } } } { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/" "" "" { en[3] } "NODE_NAME" } "" } } { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/serial.fld" "" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/serial.fld" "" "" { en[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "en\[4\] GND " "Info: Pin en\[4\] has GND driving its datain port" {  } { { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/serial.vhd" 25 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "en\[4\]" } } } } { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/" "" "" { en[4] } "NODE_NAME" } "" } } { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/serial.fld" "" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/serial.fld" "" "" { en[4] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "en\[5\] GND " "Info: Pin en\[5\] has GND driving its datain port" {  } { { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/serial.vhd" 25 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "en\[5\]" } } } } { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/" "" "" { en[5] } "NODE_NAME" } "" } } { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/serial.fld" "" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/serial.fld" "" "" { en[5] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "en\[6\] GND " "Info: Pin en\[6\] has GND driving its datain port" {  } { { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/serial.vhd" 25 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "en\[6\]" } } } } { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/" "" "" { en[6] } "NODE_NAME" } "" } } { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/serial.fld" "" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/serial.fld" "" "" { en[6] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "en\[7\] VCC " "Info: Pin en\[7\] has VCC driving its datain port" {  } { { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/serial.vhd" 25 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "en\[7\]" } } } } { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/" "" "" { en[7] } "NODE_NAME" } "" } } { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/serial.fld" "" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/serial.fld" "" "" { en[7] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "seg_data\[0\] GND " "Info: Pin seg_data\[0\] has GND driving its datain port" {  } { { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/serial.vhd" 26 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "seg_data\[0\]" } } } } { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/" "" "" { seg_data[0] } "NODE_NAME" } "" } } { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/serial.fld" "" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/serial.fld" "" "" { seg_data[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "lowbit GND " "Info: Pin lowbit has GND driving its datain port" {  } { { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/serial.vhd" 28 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lowbit" } } } } { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial_cmp.qrpt" "" { Report "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial_cmp.qrpt" Compiler "serial" "UNKNOWN" "V1" "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/db/serial.quartus_db" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/" "" "" { lowbit } "NODE_NAME" } "" } } { "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/serial.fld" "" { Floorplan "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實驗/串口/serial.fld" "" "" { lowbit } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 07 21:58:15 2008 " "Info: Processing ended: Thu Feb 07 21:58:15 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Info: Elapsed time: 00:00:11" {  } {  } 0}  } {  } 0}