{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Feb 07 21:57:55 2008 " "Info: Processing started: Thu Feb 07 21:57:55 2008" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off serial -c serial " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off serial -c serial" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "serial.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file serial.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 serial-arch " "Info: Found design unit 1: serial-arch" {  } { { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實(shí)驗(yàn)/串口/serial.vhd" 31 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 serial " "Info: Found entity 1: serial" {  } { { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實(shí)驗(yàn)/串口/serial.vhd" 19 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "serial " "Info: Elaborating entity \"serial\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "txd_buf\[7\] data_in GND " "Warning: Reduced register \"txd_buf\[7\]\" with stuck data_in port to stuck value GND" {  } { { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實(shí)驗(yàn)/串口/serial.vhd" 50 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "en\[0\] GND " "Warning: Pin \"en\[0\]\" stuck at GND" {  } { { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實(shí)驗(yàn)/串口/serial.vhd" 25 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[1\] GND " "Warning: Pin \"en\[1\]\" stuck at GND" {  } { { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實(shí)驗(yàn)/串口/serial.vhd" 25 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[2\] GND " "Warning: Pin \"en\[2\]\" stuck at GND" {  } { { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實(shí)驗(yàn)/串口/serial.vhd" 25 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[3\] GND " "Warning: Pin \"en\[3\]\" stuck at GND" {  } { { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實(shí)驗(yàn)/串口/serial.vhd" 25 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[4\] GND " "Warning: Pin \"en\[4\]\" stuck at GND" {  } { { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實(shí)驗(yàn)/串口/serial.vhd" 25 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[5\] GND " "Warning: Pin \"en\[5\]\" stuck at GND" {  } { { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實(shí)驗(yàn)/串口/serial.vhd" 25 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[6\] GND " "Warning: Pin \"en\[6\]\" stuck at GND" {  } { { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實(shí)驗(yàn)/串口/serial.vhd" 25 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[7\] VCC " "Warning: Pin \"en\[7\]\" stuck at VCC" {  } { { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實(shí)驗(yàn)/串口/serial.vhd" 25 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "seg_data\[0\] GND " "Warning: Pin \"seg_data\[0\]\" stuck at GND" {  } { { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實(shí)驗(yàn)/串口/serial.vhd" 26 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "lowbit GND " "Warning: Pin \"lowbit\" stuck at GND" {  } { { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實(shí)驗(yàn)/串口/serial.vhd" 28 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "serial.vhd" "" { Text "C:/Documents and Settings/DengBo/桌面/VHDL_Development_Board_Sources/接口實(shí)驗(yàn)/串口/serial.vhd" 48 -1 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "232 " "Info: Implemented 232 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "4 " "Info: Implemented 4 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "18 " "Info: Implemented 18 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "210 " "Info: Implemented 210 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 12 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 07 21:58:03 2008 " "Info: Processing ended: Thu Feb 07 21:58:03 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Info: Elapsed time: 00:00:08" {  } {  } 0}  } {  } 0}