?? sd_defs.h
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/*************************************************************************
*
* Copyright Mentor Graphics Corporation 2002
* All Rights Reserved.
*
* THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS
* THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS
* SUBJECT TO LICENSE TERMS.
*
*************************************************************************/
/*************************************************************************
*
* FILE NAME VERSION
*
* sd_defs.h Nucleus PLUS\ARM925\Code Composer 1.14.1
*
* COMPONENT
*
* SD - Serial Driver
*
* DESCRIPTION
*
* This file contains constant definitions and function macros
* for the Serial Driver module.
*
* DATA STRUCTURES
*
* SD_PORT : Structure to keep all needed info. about a port.
*
* DEPENDENCIES
*
* none
*
*
*************************************************************************/
#ifndef SD_DEFS_H
#define SD_DEFS_H
/**************** User configurable section *************************/
/* The default system clock 48MHz */
#define UART_CLOCK 48000000
/* The base addresses for the seperate UART registers. */
#define SD_UART1_BASE 0xFFFB0000
#define SD_UART2_BASE 0xFFFB0800
#define SD_UART1_VECTOR 46
#define SD_UART2_VECTOR 47
/* Macros for specifying which UART to use. */
#define SD_UART1 1
#define SD_UART2 2
#define SD_MAX_UARTS 2
#define ICBASE (0xFFFECB00) /* Interrupt Controller Base */
#define IRQENABLE ((volatile int *)(ICBASE + 0x18))
#define INT_MASK_OFFSET 0x04
#define INT_ITR_OFFSET 0x00
/* Defines for use by applications */
#define UART_INT_B 0x8000
#define UART_INT_A 0x4000
#define LEVEL_2_INT 0x0001
/* These use specific type names, putting the register name
in the macro, because these macros are used by port specific
sections of code and will most likely have different names
on other UARTS. */
/*************************************/
/* Receive Holding Register - RHR (R)*/
/*************************************/
#define RHR_OFFSET 0x00
/**************************************/
/* Transmit Holding Register - THR (W)*/
/**************************************/
#define THR_OFFSET 0x00
/****************************************/
/* Interrupt Enable Register - IER (R/W)*/
/****************************************/
#define IER_OFFSET 0x04
#define IER_RX_HOLDING_REG 0x01 /* bit 0 - Recieve Holding Register Interrupt
- Enabled When Set */
#define IER_TX_HOLDING_REG 0x02 /* bit 1 - Transmit Holding Register Interrupt
- Enabled When Set */
#define IER_RX_LINE_STATUS 0x04 /* bit 2 - recieve Line Status Interrupt
- Enabled When Set */
#define IER_MODEM_STATUS 0x08 /* bit 3 - Modem Status Interrupt
- Enabled When Set */
/************************************/
/* FIFO Control Register - FCR (W) */
/************************************/
#define FCR_OFFSET 0x08
#define FCR_FIFO_ENABLED 0x01 /* bit 0 - Enabled When Set */
#define FCR_RCVR_TRIG_LEVEL 0x00 /* bit 6:bit 7 - 8 Bytes Trigger Level */
#define FCR_FIFO_RESET 0x06 /* bit 1-2 - TX/RX FIFO Reset When Set */
/************************************************/
/* Interrupt Identification Register - IIR (IIR)*/
/************************************************/
#define IIR_OFFSET 0x08
#define IIR_TYPE_MASK 0x0000003E /* bit 5:bit 1 */
#define IIR_PENDING 0x00000001 /* ISR pending bit - 0=pending, 1=not pending */
#define IIR_RX_TIMEOUT 0x0000000C /* 1 1 0 - RX time out Priority 2 */
#define IIR_RX_RDY 0x00000004 /* 0 1 0 - Received Data Ready Priority 2 */
#define IIR_TX_RDY 0x00000002 /* 0 0 1 - Transmitter Holding Reg Empty Priority 3 */
#define IIR_RX_LINE_STAT 0x00000006 /* 0 1 1 - Receive Line Status Priority 1 */
/**************************************/
/* Latch Control Register - LCR (R/W)*/
/**************************************/
#define LCR_OFFSET 0x0C
#define LCR_5_BIT_WORD 0x00 /* 0 0 - 5 Bit Word */
#define LCR_6_BIT_WORD 0x01 /* 0 1 - 6 Bit Word */
#define LCR_7_BIT_WORD 0x02 /* 1 0 - 7 Bit Word */
#define LCR_8_BIT_WORD 0x03 /* 1 1 - 8 Bit Word */
#define LCR_STOP_BIT_1 0x00 /* 1 stop bit */
#define LCR_STOP_BIT_2 0x04 /* 2 stop bit */
#define LCR_PARITY_ENABLE 0x08 /* bit 3 - Enable Parity Bit Generation and Check
- Enabled When Set */
#define LCR_PARITY_DISABLE 0x00 /* bit 3 - Enable Parity Bit Generation and Check
- Enabled When Set */
#define LCR_PARITY_EVEN 0x10 /* bit 4 - Odd/Even Parity Generation and Check
- Even When Set */
#define LCR_PARITY_ODD 0x00 /* bit 4 - Odd/Even Parity Generation and Check
- Odd When Set */
#define LCR_BREAK_SET 0x40 /* bit 6 - Force Break Control ( Tx o/p low)
- Forced When Set */
#define LCR_NO_BREAK 0x00 /* bit 6 - Normal operating conditions */
#define LCR_DIV_EN 0x80 /* Enable access to DLL and DLH */
/*************************************/
/* Modem Control Register - MCR (R/W)*/
/*************************************/
#define MCR_OFFSET 0x10
#define MCR_DTR_LOW 0x01 /* bit 0 - Set DCD Signal Low/High - DCD Low when Set */
#define MCR_RTS_LOW 0x02 /* bit 1 - Set RTS Signal Low/High - RTS Low when Set */
#define MCR_NORMAL_MODE 0x00 /* bit 4 - normal operating mode */
#define MCR_LOOP_BACK 0x10 /* bit 4 - enable loopback mode */
#define MCR_TCR_TLR 0x40 /* bit 6 - enable access to TCR and TLR */
#define MCR_CLKSEL 0x80 /* bit 7 - enable clk/4 */
#define MCR_Not_Used 0x0C /* bit 2,bit 3 - not used */
/* The Following Registers are Status Registers which Report conditions within the */
/* UART/PPP during operation. The defined values are masks to ensure that the register*/
/* flags are correctly accessed */
/*********************************/
/* Line Status Register - LSR (R)*/
/*********************************/
#define LSR_OFFSET 0x14
#define LSR_RX_DATA_READY 0x01 /* bit 0 - Data Received and Saved in Holding Reg
- Set when Valid */
#define LSR_OVERRUN_ERROR 0x02 /* bit 1 - Overrun Error Occured
- Set When Valid */
#define LSR_PARITY_ERROR 0x04 /* bit 2 - Parity Error Occured
- Set When Valid */
#define LSR_FRAMING_ERROR 0x08 /* bit 3 - Framing Error Occured
- Set When Valid */
#define LSR_BREAK_ERROR 0x10 /* bit 4 - Break Error Occured
- Set When Valid */
#define LSR_TX_HOLD_EMPTY 0x20 /* bit 5 - Tx Holding Register is empty and ready
- Set When Valid */
#define LSR_TX_HOLD_FULL 0x00 /* bit 5 - Tx Holding Register is Full */
#define LSR_TX_EMPTY 0x40 /* bit 6 - 1= Tx Holding and shift registers are empty */
#define LSR_TX_FULL 0x00 /* bit 6 - 0= Tx Holding and shift registers are full */
#define LSR_FIFO_ERROR 0x80 /* bit 7 - At Least one of b4 - b2 has occurred
- Set When Valid */
/**********************************/
/* Modem Status Register - MSR (R)*/
/**********************************/
#define MSR_OFFSET 0x18
/******************************************/
/* Supplementary Status Register - SSR (R)*/
/******************************************/
#define SSR_OFFSET 0x44 /* Supplementary Status Reg Offset */
#define SSR_TX_FIFO_FULL 0x01 /* bit 0 - Tx FIFO full - Set when full */
/***************************************/
/* Mode Definition Register - MDR (R/W)*/
/***************************************/
#define MDR_OFFSET 0x20
#define MDR_UART_MODE 0x00 /* bit 2:bit 0 - 0 0 0 - Uart Mode */
#define MDR_AUTO_MODE 0x02 /* bit 2:bit 0 - 0 1 0 - AutoBaud Mode */
#define MDR_RESET_MODE 0x07 /* bit 2:bit 0 - 1 1 1 - Reset Mode */
/***********************************************/
/* Divisor for baud-rate generation - DLH (R/W)*/
/***********************************************/
#define DLH_OFFSET 0x04
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