LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY liushuideng IS
 PORT(
      CLK: IN  STD_LOGIC;
      T:OUT STD_LOGIC_VECTOR(7 DOWNTO 0 )
     );
END liushuideng;

ARCHITECTURE behave  OF liushuideng IS
     --SIGNAL LED:STD_LOGIC_VECTOR(3 DOWNTO 0);
     SIGNAL indata: STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN

PROCESS( indata )
 BEGIN    
  CASE indata IS
     WHEN "000"=>T<="01111111";
     WHEN "001"=>T<="10111111";
     WHEN "010"=>T<="11011111";
     WHEN "011"=>T<="11101111";
     WHEN "100"=>T<="11110111";
     WHEN "101"=>T<="11111011";
     WHEN "110"=>T<="11111101";
     WHEN "111"=>T<="11111110";
     WHEN OTHERS=>T<="00000000";
  END  CASE;
 END PROCESS;

PROCESS(CLK)
BEGIN
IF CLK'EVENT AND CLK='1' THEN
     indata<=indata+1;          
END IF;
END PROCESS;
END behave;