;; Frv Machine Description;; Copyright (C) 1999, 2000, 2001 Free Software Foundation, Inc.;; Contributed by Red Hat, Inc.;; This file is part of GNU CC.;; GNU CC is free software; you can redistribute it and/or modify;; it under the terms of the GNU General Public License as published by;; the Free Software Foundation; either version 2, or (at your option);; any later version.;; GNU CC is distributed in the hope that it will be useful,;; but WITHOUT ANY WARRANTY; without even the implied warranty of;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the;; GNU General Public License for more details.;; You should have received a copy of the GNU General Public License;; along with GNU CC; see the file COPYING.  If not, write to;; the Free Software Foundation, 59 Temple Place - Suite 330,;; Boston, MA 02111-1307, USA.;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.;; ::::::::::::::::::::;; ::;; :: Unspec's used;; ::;; ::::::::::::::::::::(define_constants  [(UNSPEC_BLOCKAGE		0)   (UNSPEC_CC_TO_GPR		1)   (UNSPEC_GPR_TO_CC		2)   (UNSPEC_PIC_PROLOGUE		3)   (UNSPEC_CR_LOGIC		4)   (UNSPEC_STACK_ADJUST		5)   (UNSPEC_EH_RETURN_EPILOGUE	6)]);; ::::::::::::::::::::;; ::;; :: Constraints;; ::;; ::::::::::::::::::::;; Standard Constraints;;;; `m' A memory operand is allowed, with any kind of address that the;;     machine supports in general.;;;; `o' A memory operand is allowed, but only if the address is;;     "offsettable".  This means that adding a small integer (actually, the;;     width in bytes of the operand, as determined by its machine mode) may be;;     added to the address and the result is also a valid memory address.;;;; `V' A memory operand that is not offsettable.  In other words,;;     anything that would fit the `m' constraint but not the `o' constraint.;;;; `<' A memory operand with autodecrement addressing (either;;     predecrement or postdecrement) is allowed.;;;; `>' A memory operand with autoincrement addressing (either;;     preincrement or postincrement) is allowed.;;;; `r' A register operand is allowed provided that it is in a general;;     register.;;;; `d', `a', `f', ...;;     Other letters can be defined in machine-dependent fashion to stand for;;     particular classes of registers.  `d', `a' and `f' are defined on the;;     68000/68020 to stand for data, address and floating point registers.;;;; `i' An immediate integer operand (one with constant value) is allowed.;;     This includes symbolic constants whose values will be known only at;;     assembly time.;;;; `n' An immediate integer operand with a known numeric value is allowed.;;     Many systems cannot support assembly-time constants for operands less;;     than a word wide.  Constraints for these operands should use `n' rather;;     than `i'.;;;; 'I' First machine-dependent integer constant (6 bit signed ints).;; 'J' Second machine-dependent integer constant (10 bit signed ints).;; 'K' Third machine-dependent integer constant (-2048).;; 'L' Fourth machine-dependent integer constant (16 bit signed ints).;; 'M' Fifth machine-dependent integer constant (16 bit unsigned ints).;; 'N' Sixth machine-dependent integer constant (-2047..-1).;; 'O' Seventh machine-dependent integer constant (zero).;; 'P' Eighth machine-dependent integer constant (1..2047).;;;;     Other letters in the range `I' through `P' may be defined in a;;     machine-dependent fashion to permit immediate integer operands with;;     explicit integer values in specified ranges.  For example, on the 68000,;;     `I' is defined to stand for the range of values 1 to 8.  This is the;;     range permitted as a shift count in the shift instructions.;;;; `E' An immediate floating operand (expression code `const_double') is;;     allowed, but only if the target floating point format is the same as;;     that of the host machine (on which the compiler is running).;;;; `F' An immediate floating operand (expression code `const_double') is;;     allowed.;;;; 'G' First machine-dependent const_double.;; 'H' Second machine-dependent const_double.;;;; `s' An immediate integer operand whose value is not an explicit;;     integer is allowed.;;;;     This might appear strange; if an insn allows a constant operand with a;;     value not known at compile time, it certainly must allow any known;;     value.  So why use `s' instead of `i'?  Sometimes it allows better code;;     to be generated.;;;;     For example, on the 68000 in a fullword instruction it is possible to;;     use an immediate operand; but if the immediate value is between -128 and;;     127, better code results from loading the value into a register and;;     using the register.  This is because the load into the register can be;;     done with a `moveq' instruction.  We arrange for this to happen by;;     defining the letter `K' to mean "any integer outside the range -128 to;;     127", and then specifying `Ks' in the operand constraints.;;;; `g' Any register, memory or immediate integer operand is allowed,;;     except for registers that are not general registers.;;;; `X' Any operand whatsoever is allowed, even if it does not satisfy;;     `general_operand'.  This is normally used in the constraint of a;;     `match_scratch' when certain alternatives will not actually require a;;     scratch register.;;;; `0' Match operand 0.;; `1' Match operand 1.;; `2' Match operand 2.;; `3' Match operand 3.;; `4' Match operand 4.;; `5' Match operand 5.;; `6' Match operand 6.;; `7' Match operand 7.;; `8' Match operand 8.;; `9' Match operand 9.;;;;     An operand that matches the specified operand number is allowed.  If a;;     digit is used together with letters within the same alternative, the;;     digit should come last.;;;;     This is called a "matching constraint" and what it really means is that;;     the assembler has only a single operand that fills two roles considered;;     separate in the RTL insn.  For example, an add insn has two input;;     operands and one output operand in the RTL, but on most CISC machines an;;     add instruction really has only two operands, one of them an;;     input-output operand:;;;;          addl #35,r12;;;;     Matching constraints are used in these circumstances.  More precisely,;;     the two operands that match must include one input-only operand and one;;     output-only operand.  Moreover, the digit must be a smaller number than;;     the number of the operand that uses it in the constraint.;;;;     For operands to match in a particular case usually means that they are;;     identical-looking RTL expressions.  But in a few special cases specific;;     kinds of dissimilarity are allowed.  For example, `*x' as an input;;     operand will match `*x++' as an output operand.  For proper results in;;     such cases, the output template should always use the output-operand's;;     number when printing the operand.;;;; `p' An operand that is a valid memory address is allowed.  This is for;;     "load address" and "push address" instructions.;;;;     `p' in the constraint must be accompanied by `address_operand' as the;;     predicate in the `match_operand'.  This predicate interprets the mode;;     specified in the `match_operand' as the mode of the memory reference for;;     which the address would be valid.;;;; `Q` First non constant, non register machine-dependent insns;; `R` Second non constant, non register machine-dependent insns;; `S` Third non constant, non register machine-dependent insns;; `T` Fourth non constant, non register machine-dependent insns;; `U` Fifth non constant, non register machine-dependent insns;;;;     Letters in the range `Q' through `U' may be defined in a;;     machine-dependent fashion to stand for arbitrary operand types.  The;;     machine description macro `EXTRA_CONSTRAINT' is passed the operand as;;     its first argument and the constraint letter as its second operand.;;;;     A typical use for this would be to distinguish certain types of memory;;     references that affect other insn operands.;;;;     Do not define these constraint letters to accept register references;;     (`reg'); the reload pass does not expect this and would not handle it;;     properly.;; Multiple Alternative Constraints;; `?' Disparage slightly the alternative that the `?' appears in, as a;;     choice when no alternative applies exactly.  The compiler regards this;;     alternative as one unit more costly for each `?' that appears in it.;;;; `!' Disparage severely the alternative that the `!' appears in.  This;;     alternative can still be used if it fits without reloading, but if;;     reloading is needed, some other alternative will be used.;; Constraint modifiers;; `=' Means that this operand is write-only for this instruction: the;;     previous value is discarded and replaced by output data.;;;; `+' Means that this operand is both read and written by the;;     instruction.;;;;     When the compiler fixes up the operands to satisfy the constraints, it;;     needs to know which operands are inputs to the instruction and which are;;     outputs from it.  `=' identifies an output; `+' identifies an operand;;     that is both input and output; all other operands are assumed to be;;     input only.;;;; `&' Means (in a particular alternative) that this operand is written;;     before the instruction is finished using the input operands.  Therefore,;;     this operand may not lie in a register that is used as an input operand;;     or as part of any memory address.;;;;     `&' applies only to the alternative in which it is written.  In;;     constraints with multiple alternatives, sometimes one alternative;;     requires `&' while others do not.;;;;     `&' does not obviate the need to write `='.;;;; `%' Declares the instruction to be commutative for this operand and the;;     following operand.  This means that the compiler may interchange the two;;     operands if that is the cheapest way to make all operands fit the;;     constraints.  This is often used in patterns for addition instructions;;     that really have only two operands: the result must go in one of the;;     arguments.;;;; `#' Says that all following characters, up to the next comma, are to be;;     ignored as a constraint.  They are significant only for choosing;;     register preferences.;;;; `*' Says that the following character should be ignored when choosing;;     register preferences.  `*' has no effect on the meaning of the;;     constraint as a constraint, and no effect on reloading.;; ::::::::::::::::::::;; ::;; :: Attributes;; ::;; ::::::::::::::::::::;; The `define_attr' expression is used to define each attribute required by;; the target machine.  It looks like:;;;; (define_attr NAME LIST-OF-VALUES DEFAULT);; NAME is a string specifying the name of the attribute being defined.;; LIST-OF-VALUES is either a string that specifies a comma-separated list of;; values that can be assigned to the attribute, or a null string to indicate;; that the attribute takes numeric values.;; DEFAULT is an attribute expression that gives the value of this attribute;; for insns that match patterns whose definition does not include an explicit;; value for this attribute.;; For each defined attribute, a number of definitions are written to the;; `insn-attr.h' file.  For cases where an explicit set of values is specified;; for an attribute, the following are defined:;; * A `#define' is written for the symbol `HAVE_ATTR_NAME'.;;;; * An enumeral class is defined for `attr_NAME' with elements of the;;   form `UPPER-NAME_UPPER-VALUE' where the attribute name and value are first;;   converted to upper case.;;;; * A function `get_attr_NAME' is defined that is passed an insn and;;   returns the attribute value for that insn.;; For example, if the following is present in the `md' file:;;;; (define_attr "type" "branch,fp,load,store,arith" ...);;;; the following lines will be written to the file `insn-attr.h'.;;;; #define HAVE_ATTR_type;; enum attr_type {TYPE_BRANCH, TYPE_FP, TYPE_LOAD, TYPE_STORE, TYPE_ARITH};;; extern enum attr_type get_attr_type ();;; If the attribute takes numeric values, no `enum' type will be defined and;; the function to obtain the attribute's value will return `int'.(define_attr "length" "" (const_int 4));; Processor type -- this attribute must exactly match the processor_type;; enumeration in frv-protos.h.(define_attr "cpu" "generic,fr500,fr400,fr300,simple,tomcat"  (const (symbol_ref "frv_cpu_type")));; Attribute is "yes" for branches and jumps that span too great a distance;; to be implemented in the most natural way.  Such instructions will use;; a call instruction in some way.(define_attr "far_jump" "yes,no" (const_string "no"));; Instruction type;; The table below summarises the types of media instruction and their;; scheduling classification.  Headings are:;; Type:	the name of the define_attr type;; Conditions:	"yes" if conditional variants are available;; FR500:	Fujitsu's categorisation for the FR500;; FR400:	Fujitsu's categorisation for the FR400 (but see below).;; On the FR400, media instructions are divided into 2 broad categories.;; Category 1 instructions can execute in either the M0 or M1 unit and can;; execute in parallel with other category 1 instructions.  Category 2;; instructions must use the M0 unit, and therefore cannot run in parallel;; with other media instructions.;; The FR400 documentation also divides media instructions into one of seven;; categories (m1 to m7).  m1 to m4 contain both Category 1 and Category 2;; instructions, so we use a combination of the categories here.;; Type		Conditional	FR500	FR400;; ----		----------	-----	-----;; mlogic	yes		m1	m1:1;; mrdacc	no		m2	m4:1;; mwtacc	no		m3	m5:1;; maveh	no		m1	m1:1;; msath	no		m1	m1:1;; maddh	yes		m1	m1:1;; mqaddh	yes		m1	m1:2;; mpackh	no		m2	m3:1;; munpackh	no		m2	m3:2;; mdpackh	no		m5	m3:2;; mbhconv	yes		m2	m3:2;; mrot		no		m2	m3:1;; mshift	no		m2	m3:1;; mexpdhw	yes		m2	m3:1;; mexpdhd	yes		m2	m3:2;; mwcut	no		m2	m3:2;; mmulh	yes		m4	m2:1;; mmulxh	no		m4	m2:1;; mmach	yes		m4	m2:1;; mmrdh	no		m4	m2:1;; mqmulh	yes		m4	m2:2;; mqmulxh	no		m4	m2:2;; mqmach	yes		m4	m2:2;; mcpx		yes		m4	m2:1;; mqcpx	yes		m4	m2:2;; mcut		no		m2	m4:1;; mclracc	no		m3	m4:1;; mclracca	no		m6	m4:2;; mdunpackh	no		m2	n/a;; mbhconve	no		m2	n/a;; maddacc	no		n/a	m2:1;; mdaddacc	no		n/a	m2:2;; mabsh	no		n/a	m1:1;; mdrot	no		n/a	m3:2;; mcpl		no		n/a	m3:2;; mdcut	no		n/a	m4:2;; mqsath	no		n/a	m1:2;; mset		no		n/a	m1:1