popped when returning from a subroutine call.   FUNTYPE is the data type of the function (as a tree),   or for a library call it is an identifier node for the subroutine name.   SIZE is the number of bytes of arguments passed on the stack.   On the MCore, the callee does not pop any of its arguments that were passed   on the stack.  */#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0/* Define how to find the value returned by a function.   VALTYPE is the data type of the value (as a tree).   If the precise function being called is known, FUNC is its FUNCTION_DECL;   otherwise, FUNC is 0.  */#define FUNCTION_VALUE(VALTYPE, FUNC)  mcore_function_value (VALTYPE, FUNC)/* Don't default to pcc-struct-return, because gcc is the only compiler, and   we want to retain compatibility with older gcc versions.  */#define DEFAULT_PCC_STRUCT_RETURN 0/* how we are going to return big values *//* * #define RETURN_IN_MEMORY(TYPE) \ *   (TYPE_MODE (TYPE) == BLKmode \ *    || ((TREE_CODE (TYPE) == RECORD_TYPE || TREE_CODE(TYPE) == UNION_TYPE) \ *        && !(TYPE_MODE (TYPE) == SImode \ * 	    || (TYPE_MODE (TYPE) == BLKmode \ * 		&& TYPE_ALIGN (TYPE) == BITS_PER_WORD \ * 		&& int_size_in_bytes (TYPE) == UNITS_PER_WORD)))) */ /* How many registers to use for struct return.  */#define	RETURN_IN_MEMORY(TYPE) (int_size_in_bytes (TYPE) > 2 * UNITS_PER_WORD)/* Define how to find the value returned by a library function   assuming the value has mode MODE.  */#define LIBCALL_VALUE(MODE)  gen_rtx (REG, MODE, FIRST_RET_REG)/* 1 if N is a possible register number for a function value.   On the MCore, only r4 can return results.  */#define FUNCTION_VALUE_REGNO_P(REGNO)  ((REGNO) == FIRST_RET_REG)#define	MUST_PASS_IN_STACK(MODE,TYPE)  \  mcore_must_pass_on_stack (MODE, TYPE)/* 1 if N is a possible register number for function argument passing.  */#define FUNCTION_ARG_REGNO_P(REGNO)  \  ((REGNO) >= FIRST_PARM_REG && (REGNO) < (NPARM_REGS + FIRST_PARM_REG))/* Define a data type for recording info about an argument list   during the scan of that argument list.  This data type should   hold all necessary information about the function itself   and about the args processed so far, enough to enable macros   such as FUNCTION_ARG to determine where the next arg should go.   On MCore, this is a single integer, which is a number of words   of arguments scanned so far (including the invisible argument,   if any, which holds the structure-value-address).   Thus NARGREGS or more means all following args should go on the stack.  */#define CUMULATIVE_ARGS  int#define ROUND_ADVANCE(SIZE)	\  ((SIZE + UNITS_PER_WORD - 1) / UNITS_PER_WORD)/* Round a register number up to a proper boundary for an arg of mode    MODE.       We round to an even reg for things larger than a word.  */#define ROUND_REG(X, MODE) 				\  ((TARGET_8ALIGN 					\   && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) 	\   ? ((X) + ((X) & 1)) : (X))/* Initialize a variable CUM of type CUMULATIVE_ARGS   for a call to a function whose data type is FNTYPE.   For a library call, FNTYPE is 0.   On MCore, the offset always starts at 0: the first parm reg is always   the same reg.  */#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT)  \  ((CUM) = 0)/* Update the data in CUM to advance over an argument   of mode MODE and data type TYPE.   (TYPE is null for libcalls where that information may not be   available.)  */#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)	   \ ((CUM) = (ROUND_REG ((CUM), (MODE))			   \	   + ((NAMED) * mcore_num_arg_regs (MODE, TYPE)))) \/* Define where to put the arguments to a function.  */#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \  mcore_function_arg (CUM, MODE, TYPE, NAMED)/* A C expression that indicates when an argument must be passed by   reference.  If nonzero for an argument, a copy of that argument is   made in memory and a pointer to the argument is passed instead of   the argument itself.  The pointer is passed in whatever way is   appropriate for passing a pointer to that type.  */#define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \  MUST_PASS_IN_STACK (MODE, TYPE)/* For an arg passed partly in registers and partly in memory,   this is the number of registers used.   For args passed entirely in registers or entirely in memory, zero.   Any arg that starts in the first NPARM_REGS regs but won't entirely   fit in them needs partial registers on the MCore.  */#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \  mcore_function_arg_partial_nregs (CUM, MODE, TYPE, NAMED)/* Perform any needed actions needed for a function that is receiving a   variable number of arguments.  */#define SETUP_INCOMING_VARARGS(ASF, MODE, TYPE, PAS, ST) \  mcore_setup_incoming_varargs (ASF, MODE, TYPE, & PAS)/* Call the function profiler with a given profile label.  */#define FUNCTION_PROFILER(STREAM,LABELNO)		\{							\  fprintf (STREAM, "	trap	1\n");			\  fprintf (STREAM, "	.align	2\n");			\  fprintf (STREAM, "	.long	LP%d\n", (LABELNO));	\}/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,   the stack pointer does not matter.  The value is tested only in   functions that have frame pointers.   No definition is equivalent to always zero.  */#define EXIT_IGNORE_STACK 0/* Output assembler code for a block containing the constant parts   of a trampoline, leaving space for the variable parts.   On the MCore, the trapoline looks like:   	lrw	r1,  function     	lrw	r13, area   	jmp	r13   	or	r0, r0    .literals                                                */#define TRAMPOLINE_TEMPLATE(FILE)  		\{						\  fprintf ((FILE), "	.short	0x7102\n");	\  fprintf ((FILE), "	.short	0x7d02\n");	\  fprintf ((FILE), "	.short	0x00cd\n");     \  fprintf ((FILE), "	.short	0x1e00\n");	\  fprintf ((FILE), "	.long	0\n");		\  fprintf ((FILE), "	.long	0\n");		\}/* Length in units of the trampoline for entering a nested function.  */#define TRAMPOLINE_SIZE  12/* Alignment required for a trampoline in bits.  */#define TRAMPOLINE_ALIGNMENT  32/* Emit RTL insns to initialize the variable parts of a trampoline.   FNADDR is an RTX for the address of the function's pure code.   CXT is an RTX for the static chain value for the function.  */#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT)  \{									\  emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 8)),	\		  (CXT));						\  emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 12)),	\		  (FNADDR));						\}/* Macros to check register numbers against specific register classes.  *//* These assume that REGNO is a hard or pseudo reg number.   They give nonzero only if REGNO is a hard reg of the suitable class   or a pseudo reg currently allocated to a suitable hard reg.   Since they use reg_renumber, they are safe only once reg_renumber   has been allocated, which happens in local-alloc.c.  */#define REGNO_OK_FOR_BASE_P(REGNO)  \  ((REGNO) < AP_REG || (unsigned) reg_renumber[(REGNO)] < AP_REG)#define REGNO_OK_FOR_INDEX_P(REGNO)   0/* Maximum number of registers that can appear in a valid memory    address.  */#define MAX_REGS_PER_ADDRESS 1/* Recognize any constant value that is a valid address.  */#define CONSTANT_ADDRESS_P(X) 	 (GET_CODE (X) == LABEL_REF)/* Nonzero if the constant value X is a legitimate general operand.   It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.   On the MCore, allow anything but a double.  */#define LEGITIMATE_CONSTANT_P(X) (GET_CODE(X) != CONST_DOUBLE)#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN)/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx   and check its validity for a certain class.   We have two alternate definitions for each of them.   The usual definition accepts all pseudo regs; the other rejects   them unless they have been allocated suitable hard regs.   The symbol REG_OK_STRICT causes the latter definition to be used.  */#ifndef REG_OK_STRICT/* Nonzero if X is a hard reg that can be used as a base reg   or if it is a pseudo reg.  */#define REG_OK_FOR_BASE_P(X) \    	(REGNO (X) <= 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER)/* Nonzero if X is a hard reg that can be used as an index   or if it is a pseudo reg.  */#define REG_OK_FOR_INDEX_P(X)	0#else/* Nonzero if X is a hard reg that can be used as a base reg.  */#define REG_OK_FOR_BASE_P(X)	\	REGNO_OK_FOR_BASE_P (REGNO (X))/* Nonzero if X is a hard reg that can be used as an index.  */#define REG_OK_FOR_INDEX_P(X)	0#endif/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression   that is a valid memory address for an instruction.   The MODE argument is the machine mode for the MEM expression   that wants to use this address.   The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS.  */#define BASE_REGISTER_RTX_P(X)  \  (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))#define INDEX_REGISTER_RTX_P(X)  \  (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X))/* Jump to LABEL if X is a valid address RTX.  This must also take   REG_OK_STRICT into account when deciding about valid registers, but it uses   the above macros so we are in luck.      Allow  REG	  REG+disp    A legitimate index for a QI is 0..15, for HI is 0..30, for SI is 0..60,   and for DI is 0..56 because we use two SI loads, etc.  */#define GO_IF_LEGITIMATE_INDEX(MODE, REGNO, OP, LABEL)			\  do									\    {									\      if (GET_CODE (OP) == CONST_INT) 					\        {								\	  if (GET_MODE_SIZE (MODE) >= 4					\	      && (((unsigned)INTVAL (OP)) % 4) == 0			\	      &&  ((unsigned)INTVAL (OP)) <= 64 - GET_MODE_SIZE (MODE))	\	    goto LABEL;							\	  if (GET_MODE_SIZE (MODE) == 2 				\	      && (((unsigned)INTVAL (OP)) % 2) == 0			\	      &&  ((unsigned)INTVAL (OP)) <= 30)			\	    goto LABEL;							\	  if (GET_MODE_SIZE (MODE) == 1 				\	      && ((unsigned)INTVAL (OP)) <= 15)				\	    goto LABEL;							\        }								\    }									\  while (0)#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL)                  \{ 								  \  if (BASE_REGISTER_RTX_P (X))					  \    goto LABEL;							  \  else if (GET_CODE (X) == PLUS || GET_CODE (X) == LO_SUM) 	  \    {								  \      rtx xop0 = XEXP (X,0);					  \      rtx xop1 = XEXP (X,1);					  \      if (BASE_REGISTER_RTX_P (xop0))				  \	GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \      if (BASE_REGISTER_RTX_P (xop1))				  \	GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \    }								  \}								   								   /* Go to LABEL if ADDR (a legitimate address expression)   has an effect that depends on the machine mode it is used for.  */#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)  \{									\  if (   GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC	\      || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC)	\    goto LABEL;								\}/* Specify the machine mode that this machine uses   for the index in the tablejump instruction.  */#define CASE_VECTOR_MODE SImode/* Define this if the tablejump instruction expects the table   to contain offsets from the address of the table.   Do not define this if the table should contain absolute addresses.  *//* #define CASE_VECTOR_PC_RELATIVE *//* 'char' is signed by default.  */#define DEFAULT_SIGNED_CHAR  0/* The type of size_t unsigned int.  */#define SIZE_TYPE "unsigned int"/* Don't cse the address of the function being compiled.  */#define NO_RECURSIVE_FUNCTION_CSE 1/* Max number of bytes we can move from memory to memory   in one reasonably fast instruction.  */#define MOVE_MAX 4/* Define if operations between registers always perform the operation   on the full register even if a narrower mode is specified.  */#define WORD_REGISTER_OPERATIONS/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD   will either zero-extend or sign-extend.  The value of this macro should   be the code that says which one of the two operations is implicitly   done, NIL if none.  */#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND/* Nonzero if access to memory by bytes is slow and undesirable.  */#define SLOW_BYTE_ACCESS TARGET_SLOW_BYTES/* We assume that the store-condition-codes instructions store 0 for false   and some other value for true.  This is the value stored for true.  */#define STORE_FLAG_VALUE 1/* Immediate shift counts are truncated by the output routines (or was it   the assembler?).  Shift counts in a register are truncated by ARM.  Note   that the native compiler puts too large (> 32) immediate shift counts   into a register and shifts by the register, letting the ARM decide what   to do instead of doing that itself.  */