;; e500 SPE description;; Copyright (C) 2002 Free Software Foundation, Inc.;; Contributed by Aldy Hernandez (aldy@quesejoda.com);; This file is part of GNU CC.;; GNU CC is free software; you can redistribute it and/or modify;; it under the terms of the GNU General Public License as published by;; the Free Software Foundation; either version 2, or (at your option);; any later version.;; GNU CC is distributed in the hope that it will be useful,;; but WITHOUT ANY WARRANTY; without even the implied warranty of;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the;; GNU General Public License for more details.;; You should have received a copy of the GNU General Public License;; along with GNU CC; see the file COPYING.  If not, write to;; the Free Software Foundation, 59 Temple Place - Suite 330,;; Boston, MA 02111-1307, USA.(define_constants  [(SPE_ACC_REGNO	111)   (SPEFSCR_REGNO	112)])(define_insn "*negsf2_gpr"  [(set (match_operand:SF 0 "gpc_reg_operand" "=r")        (neg:SF (match_operand:SF 1 "gpc_reg_operand" "r")))]  "TARGET_HARD_FLOAT && !TARGET_FPRS"  "efsneg %0,%1"  [(set_attr "type" "fp")])(define_insn "*abssf2_gpr"  [(set (match_operand:SF 0 "gpc_reg_operand" "=r")	(abs:SF (match_operand:SF 1 "gpc_reg_operand" "r")))]  "TARGET_HARD_FLOAT && !TARGET_FPRS"  "efsabs %0,%1"  [(set_attr "type" "fp")])(define_insn "*addsf3_gpr"  [(set (match_operand:SF 0 "gpc_reg_operand" "=r")	(plus:SF (match_operand:SF 1 "gpc_reg_operand" "%r")		 (match_operand:SF 2 "gpc_reg_operand" "r")))]  "TARGET_HARD_FLOAT && !TARGET_FPRS"  "efsadd %0,%1,%2"  [(set_attr "type" "fp")])(define_insn "*subsf3_gpr"  [(set (match_operand:SF 0 "gpc_reg_operand" "=r")	(minus:SF (match_operand:SF 1 "gpc_reg_operand" "r")		  (match_operand:SF 2 "gpc_reg_operand" "r")))]  "TARGET_HARD_FLOAT && !TARGET_FPRS"  "efssub %0,%1,%2"  [(set_attr "type" "fp")])(define_insn "*mulsf3_gpr"  [(set (match_operand:SF 0 "gpc_reg_operand" "=r")        (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%r")                 (match_operand:SF 2 "gpc_reg_operand" "r")))]  "TARGET_HARD_FLOAT && !TARGET_FPRS"  "efsmul %0,%1,%2"  [(set_attr "type" "fp")])(define_insn "*divsf3_gpr"  [(set (match_operand:SF 0 "gpc_reg_operand" "=r")        (div:SF (match_operand:SF 1 "gpc_reg_operand" "r")                (match_operand:SF 2 "gpc_reg_operand" "r")))]  "TARGET_HARD_FLOAT && !TARGET_FPRS"  "efsdiv %0,%1,%2"  [(set_attr "type" "fp")])(define_insn "spe_efsctuiz"  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")        (unspec:SI [(match_operand:SF 1 "gpc_reg_operand" "r")] 700))]  "TARGET_HARD_FLOAT && !TARGET_FPRS"  "efsctuiz %0,%1"  [(set_attr "type" "fp")])(define_insn "spe_fixunssfsi2"  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")	(unsigned_fix:SI (fix:SF (match_operand:SF 1 "gpc_reg_operand" "r"))))]  "TARGET_HARD_FLOAT && !TARGET_FPRS"  "efsctui %0,%1"  [(set_attr "type" "fp")])(define_insn "spe_fix_truncsfsi2"  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")	(fix:SI (match_operand:SF 1 "gpc_reg_operand" "r")))]  "TARGET_HARD_FLOAT && !TARGET_FPRS"  "efsctsi %0,%1"  [(set_attr "type" "fp")])(define_insn "spe_floatunssisf2"  [(set (match_operand:SF 0 "gpc_reg_operand" "=r")        (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "r")))]  "TARGET_HARD_FLOAT && !TARGET_FPRS"  "efscfui %0,%1"  [(set_attr "type" "fp")])(define_insn "spe_floatsisf2"  [(set (match_operand:SF 0 "gpc_reg_operand" "=r")        (float:SF (match_operand:SI 1 "gpc_reg_operand" "r")))]  "TARGET_HARD_FLOAT && !TARGET_FPRS"  "efscfsi %0,%1"  [(set_attr "type" "fp")]);; SPE SIMD instructions(define_insn "spe_evabs"  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")	(abs:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")))]  "TARGET_SPE"  "evabs %0,%1"  [(set_attr "type" "vecsimple")   (set_attr  "length" "4")])(define_insn "spe_evandc"  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")        (and:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")		  (not:V2SI (match_operand:V2SI 2 "gpc_reg_operand" "r"))))]  "TARGET_SPE"  "evandc %0,%1,%2"  [(set_attr "type" "vecsimple")   (set_attr  "length" "4")])(define_insn "spe_evand"  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")        (and:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")		  (match_operand:V2SI 2 "gpc_reg_operand" "r")))]  "TARGET_SPE"  "evand %0,%1,%2"  [(set_attr "type" "vecsimple")   (set_attr  "length" "4")]);; Vector compare instructions(define_insn "spe_evcmpeq"  [(set (match_operand:CC 0 "cc_reg_operand" "=y")	(unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r")		      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 500))]  "TARGET_SPE"  "evcmpeq %0,%1,%2"  [(set_attr "type" "veccmp")   (set_attr  "length" "4")])(define_insn "spe_evcmpgts"  [(set (match_operand:CC 0 "cc_reg_operand" "=y")        (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r")		      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 501))]  "TARGET_SPE"  "evcmpgts %0,%1,%2"  [(set_attr "type" "veccmp")   (set_attr  "length" "4")])(define_insn "spe_evcmpgtu"  [(set (match_operand:CC 0 "cc_reg_operand" "=y")        (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r")		      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 502))]  "TARGET_SPE"  "evcmpgtu %0,%1,%2"  [(set_attr "type" "veccmp")   (set_attr  "length" "4")])(define_insn "spe_evcmplts"  [(set (match_operand:CC 0 "cc_reg_operand" "=y")        (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r")		      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 503))]  "TARGET_SPE"  "evcmplts %0,%1,%2"  [(set_attr "type" "veccmp")   (set_attr  "length" "4")])(define_insn "spe_evcmpltu"  [(set (match_operand:CC 0 "cc_reg_operand" "=y")        (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r")		      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 504))]  "TARGET_SPE"  "evcmpltu %0,%1,%2"  [(set_attr "type" "veccmp")   (set_attr  "length" "4")]);; Floating point vector compare instructions(define_insn "spe_evfscmpeq"  [(set (match_operand:CC 0 "cc_reg_operand" "=y")        (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")		    (match_operand:V2SF 2 "gpc_reg_operand" "r")] 538))   (clobber (reg:SI SPEFSCR_REGNO))]  "TARGET_SPE"  "evfscmpeq %0,%1,%2"  [(set_attr "type" "veccmp")   (set_attr  "length" "4")])(define_insn "spe_evfscmpgt"  [(set (match_operand:CC 0 "cc_reg_operand" "=y")        (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")		    (match_operand:V2SF 2 "gpc_reg_operand" "r")] 539))   (clobber (reg:SI SPEFSCR_REGNO))]  "TARGET_SPE"  "evfscmpgt %0,%1,%2"  [(set_attr "type" "veccmp")   (set_attr  "length" "4")])(define_insn "spe_evfscmplt"  [(set (match_operand:CC 0 "cc_reg_operand" "=y")        (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")		    (match_operand:V2SF 2 "gpc_reg_operand" "r")] 540))   (clobber (reg:SI SPEFSCR_REGNO))]  "TARGET_SPE"  "evfscmplt %0,%1,%2"  [(set_attr "type" "veccmp")   (set_attr  "length" "4")])(define_insn "spe_evfststeq"  [(set (match_operand:CC 0 "cc_reg_operand" "=y")        (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")		    (match_operand:V2SF 2 "gpc_reg_operand" "r")] 541))]  "TARGET_SPE"  "evfststeq %0,%1,%2"  [(set_attr "type" "veccmp")   (set_attr  "length" "4")])(define_insn "spe_evfststgt"  [(set (match_operand:CC 0 "cc_reg_operand" "=y")        (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")		    (match_operand:V2SF 2 "gpc_reg_operand" "r")] 542))]  "TARGET_SPE"  "evfststgt %0,%1,%2"  [(set_attr "type" "veccmp")   (set_attr  "length" "4")])(define_insn "spe_evfststlt"  [(set (match_operand:CC 0 "cc_reg_operand" "=y")        (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")		    (match_operand:V2SF 2 "gpc_reg_operand" "r")] 543))]  "TARGET_SPE"  "evfststlt %0,%1,%2"  [(set_attr "type" "veccmp")   (set_attr  "length" "4")]);; End of vector compare instructions(define_insn "spe_evcntlsw"  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 505))]  "TARGET_SPE"  "evcntlsw %0,%1"  [(set_attr "type" "vecsimple")   (set_attr  "length" "4")])(define_insn "spe_evcntlzw"  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 506))]  "TARGET_SPE"  "evcntlzw %0,%1"  [(set_attr "type" "vecsimple")   (set_attr  "length" "4")])(define_insn "spe_eveqv"  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")        (not:V2SI (xor:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")			    (match_operand:V2SI 2 "gpc_reg_operand" "r"))))]  "TARGET_SPE"  "eveqv %0,%1,%2"  [(set_attr "type" "vecsimple")   (set_attr  "length" "4")])(define_insn "spe_evextsb"  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")	(unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 507))]  "TARGET_SPE"  "evextsb %0,%1"  [(set_attr "type" "vecsimple")   (set_attr  "length" "4")])(define_insn "spe_evextsh"  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 508))]  "TARGET_SPE"  "evextsh %0,%1"  [(set_attr "type" "vecsimple")   (set_attr  "length" "4")])(define_insn "spe_evlhhesplat"  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")	(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")			   (match_operand:QI 2 "immediate_operand" "i"))))   (unspec [(const_int 0)] 509)]  "TARGET_SPE"  "evlhhesplat %0,%1,%2"  [(set_attr "type" "vecload")   (set_attr  "length" "4")])(define_insn "spe_evlhhesplatx"  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")	(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")			   (match_operand:SI 2 "gpc_reg_operand" "r"))))   (unspec [(const_int 0)] 510)]  "TARGET_SPE"  "evlhhesplatx %0,%1,%2"  [(set_attr "type" "vecload")   (set_attr  "length" "4")])(define_insn "spe_evlhhossplat"  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")	(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")			   (match_operand:QI 2 "immediate_operand" "i"))))   (unspec [(const_int 0)] 511)]  "TARGET_SPE"  "evlhhossplat %0,%1,%2"  [(set_attr "type" "vecload")   (set_attr  "length" "4")])(define_insn "spe_evlhhossplatx"  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")	(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")			   (match_operand:SI 2 "gpc_reg_operand" "r"))))   (unspec [(const_int 0)] 512)]  "TARGET_SPE"  "evlhhossplatx %0,%1,%2"  [(set_attr "type" "vecload")   (set_attr  "length" "4")])(define_insn "spe_evlhhousplat"  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")	(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")			   (match_operand:QI 2 "immediate_operand" "i"))))   (unspec [(const_int 0)] 513)]  "TARGET_SPE"  "evlhhousplat %0,%1,%2"  [(set_attr "type" "vecload")   (set_attr  "length" "4")])(define_insn "spe_evlhhousplatx"  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")	(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")			   (match_operand:SI 2 "gpc_reg_operand" "r"))))   (unspec [(const_int 0)] 514)]  "TARGET_SPE"  "evlhhousplatx %0,%1,%2"  [(set_attr "type" "vecload")   (set_attr  "length" "4")])(define_insn "spe_evlwhsplat"  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")	(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")			   (match_operand:QI 2 "immediate_operand" "i"))))   (unspec [(const_int 0)] 515)]  "TARGET_SPE"  "evlwhsplat %0,%1,%2"  [(set_attr "type" "vecload")   (set_attr  "length" "4")])(define_insn "spe_evlwhsplatx"  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")	(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")			   (match_operand:SI 2 "gpc_reg_operand" "r"))))   (unspec [(const_int 0)] 516)]  "TARGET_SPE"  "evlwhsplatx %0,%1,%2"  [(set_attr "type" "vecload")   (set_attr  "length" "4")])(define_insn "spe_evlwwsplat"  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")	(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")			   (match_operand:QI 2 "immediate_operand" "i"))))   (unspec [(const_int 0)] 517)]  "TARGET_SPE"  "evlwwsplat %0,%1,%2"  [(set_attr "type" "vecload")   (set_attr  "length" "4")])(define_insn "spe_evlwwsplatx"  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")	(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")