?? dsp281x_ev.h
字號:
};
/* Allow access to the bit fields or entire register */
union CAPCONB_REG {
Uint16 all;
struct CAPCONB_BITS bit;
};
/* Capture FIFO Status Register bit definitions */
struct CAPFIFOA_BITS {
Uint16 rsvd1:8; // 7:0 reserved
Uint16 CAP1FIFO:2; // 9:8 CAP1 FIFO status
Uint16 CAP2FIFO:2; // 11:10 CAP2 FIFO status
Uint16 CAP3FIFO:2; // 13:12 CAP2 FIFO status
Uint16 rsvd2:2; // 15:14 reserved
};
/* Allow access to the bit fields or entire register */
union CAPFIFOA_REG {
Uint16 all;
struct CAPFIFOA_BITS bit;
};
/* Capture FIFO Status Register bit definitions */
struct CAPFIFOB_BITS {
Uint16 rsvd1:8; // 7:0 reserved
Uint16 CAP4FIFO:2; // 9:8 CAP4 FIFO status
Uint16 CAP5FIFO:2; // 11:10 CAP5 FIFO status
Uint16 CAP6FIFO:2; // 13:12 CAP6 FIFO status
Uint16 rsvd2:2; // 15:14 reserved
};
/* Allow access to the bit fields or entire register */
union CAPFIFOB_REG {
Uint16 all;
struct CAPFIFOB_BITS bit;
};
/* Interrupt Mask Register bit definitions */
struct EVAIMRA_BITS {
Uint16 PDPINTA:1; // 0 Enable PDPINTA
Uint16 CMP1INT:1; // 1 Enable
Uint16 CMP2INT:1; // 2 Enable
Uint16 CMP3INT:1; // 3 Enable
Uint16 rsvd1:3; // 6:4 reserved
Uint16 T1PINT:1; // 7 Enable
Uint16 T1CINT:1; // 8 Enable
Uint16 T1UFINT:1; // 9 Enable
Uint16 T1OFINT:1; // 10 Enable
Uint16 rsvd2:5; // 15:11 reserved
};
/* Allow access to the bit fields or entire register */
union EVAIMRA_REG {
Uint16 all;
struct EVAIMRA_BITS bit;
};
/* Interrupt Mask Register bit definitions */
struct EVBIMRA_BITS {
Uint16 PDPINTB:1; // 0 Enable PDPINTB
Uint16 CMP4INT:1; // 1 Enable
Uint16 CMP5INT:1; // 2 Enable
Uint16 CMP6INT:1; // 3 Enable
Uint16 rsvd1:3; // 6:4 reserved
Uint16 T3PINT:1; // 7 Enable
Uint16 T3CINT:1; // 8 Enable
Uint16 T3UFINT:1; // 9 Enable
Uint16 T3OFINT:1; // 10 Enable
Uint16 rsvd2:5; // 15:11 reserved
};
/* Allow access to the bit fields or entire register */
union EVBIMRA_REG {
Uint16 all;
struct EVBIMRA_BITS bit;
};
struct EVAIMRB_BITS {
Uint16 T2PINT:1; // 0 Enable
Uint16 T2CINT:1; // 1 Enable
Uint16 T2UFINT:1; // 2 Enable
Uint16 T2OFINT:1; // 3 Enable
Uint16 rsvd1:12; // 15:4 reserved
};
/* Allow access to the bit fields or entire register */
union EVAIMRB_REG {
Uint16 all;
struct EVAIMRB_BITS bit;
};
struct EVBIMRB_BITS {
Uint16 T4PINT:1; // 0 Enable
Uint16 T4CINT:1; // 1 Enable
Uint16 T4UFINT:1; // 2 Enable
Uint16 T4OFINT:1; // 3 Enable
Uint16 rsvd1:12; // 15:4 reserved
};
/* Allow access to the bit fields or entire register */
union EVBIMRB_REG {
Uint16 all;
struct EVBIMRB_BITS bit;
};
struct EVAIMRC_BITS {
Uint16 CAP1INT:1; // 0 Enable
Uint16 CAP2INT:1; // 1 Enable
Uint16 CAP3INT:1; // 2 Enable
Uint16 rsvd1:13; // 15:3 reserved
};
/* Allow access to the bit fields or entire register */
union EVAIMRC_REG {
Uint16 all;
struct EVAIMRC_BITS bit;
};
struct EVBIMRC_BITS {
Uint16 CAP4INT:1; // 0 Enable
Uint16 CAP5INT:1; // 1 Enable
Uint16 CAP6INT:1; // 2 Enable
Uint16 rsvd1:13; // 15:3 reserved
};
/* Allow access to the bit fields or entire register */
union EVBIMRC_REG {
Uint16 all;
struct EVBIMRC_BITS bit;
};
/* Interrupt Flag Register bit definitions */
struct EVAIFRA_BITS {
Uint16 PDPINTA:1; // 0 Flag PDPINTA
Uint16 CMP1INT:1; // 1 Flag
Uint16 CMP2INT:1; // 2 Flag
Uint16 CMP3INT:1; // 3 Flag
Uint16 rsvd1:3; // 6:4 reserved
Uint16 T1PINT:1; // 7 Flag
Uint16 T1CINT:1; // 8 Flag
Uint16 T1UFINT:1; // 9 Flag
Uint16 T1OFINT:1; // 10 Flag
Uint16 rsvd2:5; // 15:11 reserved
};
/* Allow access to the bit fields or entire register */
union EVAIFRA_REG {
Uint16 all;
struct EVAIMRA_BITS bit;
};
/* Interrupt Mask Register bit definitions */
struct EVBIFRA_BITS {
Uint16 PDPINTB:1; // 0 Flag PDPINTB
Uint16 CMP4INT:1; // 1 Flag
Uint16 CMP5INT:1; // 2 Flag
Uint16 CMP6INT:1; // 3 Flag
Uint16 rsvd1:3; // 6:4 reserved
Uint16 T3PINT:1; // 7 Flag
Uint16 T3CINT:1; // 8 Flag
Uint16 T3UFINT:1; // 9 Flag
Uint16 T3OFINT:1; // 10 Flag
Uint16 rsvd2:5; // 15:11 reserved
};
/* Allow access to the bit fields or entire register */
union EVBIFRA_REG {
Uint16 all;
struct EVBIFRA_BITS bit;
};
struct EVAIFRB_BITS {
Uint16 T2PINT:1; // 0 Flag
Uint16 T2CINT:1; // 1 Flag
Uint16 T2UFINT:1; // 2 Flag
Uint16 T2OFINT:1; // 3 Flag
Uint16 rsvd1:12; // 15:4 reserved
};
/* Allow access to the bit fields or entire register */
union EVAIFRB_REG {
Uint16 all;
struct EVAIFRB_BITS bit;
};
struct EVBIFRB_BITS {
Uint16 T4PINT:1; // 0 Flag
Uint16 T4CINT:1; // 1 Flag
Uint16 T4UFINT:1; // 2 Flag
Uint16 T4OFINT:1; // 3 Flag
Uint16 rsvd1:12; // 15:4 reserved
};
/* Allow access to the bit fields or entire register */
union EVBIFRB_REG {
Uint16 all;
struct EVBIFRB_BITS bit;
};
struct EVAIFRC_BITS {
Uint16 CAP1INT:1; // 0 Flag
Uint16 CAP2INT:1; // 1 Flag
Uint16 CAP3INT:1; // 2 Flag
Uint16 rsvd1:13; // 15:3 reserved
};
/* Allow access to the bit fields or entire register */
union EVAIFRC_REG {
Uint16 all;
struct EVAIFRC_BITS bit;
};
struct EVBIFRC_BITS {
Uint16 CAP4INT:1; // 0 Flag
Uint16 CAP5INT:1; // 1 Flag
Uint16 CAP6INT:1; // 2 Flag
Uint16 rsvd1:13; // 15:3 reserved
};
/* Allow access to the bit fields or entire register */
union EVBIFRC_REG {
Uint16 all;
struct EVBIFRC_BITS bit;
};
/* EVA Register File */
struct EVA_REGS {
union GPTCONA_REG GPTCONA; //0x7400
Uint16 T1CNT; //0x7401
Uint16 T1CMPR; //0x7402
Uint16 T1PR; //0x7403
union T1CON_REG T1CON; //0x7404
Uint16 T2CNT; //0x7405
Uint16 T2CMPR; //0x7406
Uint16 T2PR; //0x7407
union T2CON_REG T2CON; //0x7408
union EXTCONA_REG EXTCONA; //0x7409
Uint16 rsvd1[7]; //0x740A-10
union COMCONA_REG COMCONA; //0x7411
Uint16 rsvd2; //0x7412
union ACTRA_REG ACTRA; //0x7413
Uint16 rsvd3; //0x7414
union DBTCON_REG DBTCONA; //0x7415
Uint16 rsvd4; //0x7416
Uint16 CMPR1; //0x7417
Uint16 CMPR2; //0x7418
Uint16 CMPR3; //0x7419
Uint16 rsvd5[6]; //0x741A-F
union CAPCONA_REG CAPCONA; //0x7420
Uint16 rsvd6; //0x7421
union CAPFIFOA_REG CAPFIFOA; //0x7422
Uint16 CAP1FIFO; //0x7423
Uint16 CAP2FIFO; //0x7424
Uint16 CAP3FIFO; //0x7425
Uint16 rsvd7; //0x7426
Uint16 CAP1FBOT; //0x7427
Uint16 CAP2FBOT; //0x7428
Uint16 CAP3FBOT; //0x7429
Uint16 rsvd8[2]; //0x742A-B
union EVAIMRA_REG EVAIMRA; //0x742C
union EVAIMRB_REG EVAIMRB; //0x742D
union EVAIMRC_REG EVAIMRC; //0x742E
union EVAIFRA_REG EVAIFRA; //0x742F
union EVAIFRB_REG EVAIFRB; //0x7430
union EVAIFRC_REG EVAIFRC; //0x7431
};
/* EVB Register File */
struct EVB_REGS {
union GPTCONB_REG GPTCONB; //0x7500
Uint16 T3CNT; //0x7501
Uint16 T3CMPR; //0x7502
Uint16 T3PR; //0x7503
union T3CON_REG T3CON; //0x7504
Uint16 T4CNT; //0x7505
Uint16 T4CMPR; //0x7506
Uint16 T4PR; //0x7507
union T4CON_REG T4CON; //0x7508
union EXTCONB_REG EXTCONB; //0x7509
Uint16 rsvd1[7]; //0x750A-10
union COMCONB_REG COMCONB; //0x7511
Uint16 rsvd2; //0x7512
union ACTRB_REG ACTRB; //0x7513
Uint16 rsvd3; //0x7514
union DBTCON_REG DBTCONB; //0x7515
Uint16 rsvd4; //0x7516
Uint16 CMPR4; //0x7517
Uint16 CMPR5; //0x7518
Uint16 CMPR6; //0x7519
Uint16 rsvd5[6]; //0x751A-F
union CAPCONB_REG CAPCONB; //0x7520
Uint16 rsvd6; //0x7521
union CAPFIFOB_REG CAPFIFOB; //0x7522
Uint16 CAP4FIFO; //0x7523
Uint16 CAP5FIFO; //0x7524
Uint16 CAP6FIFO; //0x7525
Uint16 rsvd7; //0x7526
Uint16 CAP4FBOT; //0x7527
Uint16 CAP5FBOT; //0x7528
Uint16 rsvd8[2]; //0x752A-B
union EVBIMRA_REG EVBIMRA; //0x752C
union EVBIMRB_REG EVBIMRB; //0x752D
union EVBIMRC_REG EVBIMRC; //0x752E
union EVBIFRA_REG EVBIFRA; //0x752F
union EVBIFRB_REG EVBIFRB; //0x7530
union EVBIFRC_REG EVBIFRC; //0x7531
};
//---------------------------------------------------------------------------
// Function prototypes and external definitions:
//
extern volatile struct EVA_REGS EvaRegs;
extern volatile struct EVB_REGS EvbRegs;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP281x_EV.H definition
//===========================================================================
// No more.
//===========================================================================
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