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?? xianshi.map.rpt

?? 這是一個給予FPGA的動態顯示代碼
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+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                       ;
+-------------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+
; Compilation Hierarchy Node                ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name                                                    ;
+-------------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+
; |xianshi                                  ; 99 (0)      ; 75           ; 0           ; 74   ; 24 (0)       ; 48 (0)            ; 27 (0)           ; 9 (0)           ; 0 (0)      ; |xianshi                                                               ;
;    |drive:comb_5|                         ; 36 (35)     ; 17           ; 0           ; 0    ; 19 (19)      ; 0 (0)             ; 17 (16)          ; 0 (0)           ; 0 (0)      ; |xianshi|drive:comb_5                                                  ;
;       |dc:comb_4|                         ; 1 (1)       ; 1            ; 0           ; 0    ; 0 (0)        ; 0 (0)             ; 1 (1)            ; 0 (0)           ; 0 (0)      ; |xianshi|drive:comb_5|dc:comb_4                                        ;
;    |led_latcha:comb_6|                    ; 51 (51)     ; 48           ; 0           ; 0    ; 3 (3)        ; 48 (48)           ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |xianshi|led_latcha:comb_6                                             ;
;    |tim:comb_4|                           ; 12 (3)      ; 10           ; 0           ; 0    ; 2 (2)        ; 0 (0)             ; 10 (1)           ; 9 (0)           ; 0 (0)      ; |xianshi|tim:comb_4                                                    ;
;       |lpm_counter:a_rtl_0|               ; 9 (0)       ; 9            ; 0           ; 0    ; 0 (0)        ; 0 (0)             ; 9 (0)            ; 9 (0)           ; 0 (0)      ; |xianshi|tim:comb_4|lpm_counter:a_rtl_0                                ;
;          |alt_counter_f10ke:wysi_counter| ; 9 (9)       ; 9            ; 0           ; 0    ; 0 (0)        ; 0 (0)             ; 9 (9)            ; 9 (9)           ; 0 (0)      ; |xianshi|tim:comb_4|lpm_counter:a_rtl_0|alt_counter_f10ke:wysi_counter ;
+-------------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 75    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 57    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 48    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+---------------------------------------------------+
; Inverted Register Statistics                      ;
+-----------------------------------------+---------+
; Inverted Register                       ; Fan out ;
+-----------------------------------------+---------+
; led_latcha:comb_6|red_data[0]           ; 1       ;
; led_latcha:comb_6|red_data[1]           ; 1       ;
; led_latcha:comb_6|red_data[2]           ; 1       ;
; led_latcha:comb_6|red_data[3]           ; 1       ;
; led_latcha:comb_6|red_data[4]           ; 1       ;
; led_latcha:comb_6|red_data[5]           ; 1       ;
; led_latcha:comb_6|red_data[6]           ; 1       ;
; led_latcha:comb_6|red_data[7]           ; 1       ;
; led_latcha:comb_6|red_data[8]           ; 1       ;
; led_latcha:comb_6|red_data[9]           ; 1       ;
; led_latcha:comb_6|red_data[10]          ; 1       ;
; led_latcha:comb_6|red_data[11]          ; 1       ;
; led_latcha:comb_6|red_data[12]          ; 1       ;
; led_latcha:comb_6|red_data[13]          ; 1       ;
; led_latcha:comb_6|red_data[14]          ; 1       ;
; led_latcha:comb_6|red_data[15]          ; 1       ;
; led_latcha:comb_6|grn_data[0]           ; 1       ;
; led_latcha:comb_6|grn_data[1]           ; 1       ;
; led_latcha:comb_6|grn_data[2]           ; 1       ;
; led_latcha:comb_6|grn_data[3]           ; 1       ;
; led_latcha:comb_6|grn_data[4]           ; 1       ;
; led_latcha:comb_6|grn_data[5]           ; 1       ;
; led_latcha:comb_6|grn_data[6]           ; 1       ;
; led_latcha:comb_6|grn_data[7]           ; 1       ;
; led_latcha:comb_6|grn_data[8]           ; 1       ;
; led_latcha:comb_6|grn_data[9]           ; 1       ;
; led_latcha:comb_6|grn_data[10]          ; 1       ;
; led_latcha:comb_6|grn_data[11]          ; 1       ;
; led_latcha:comb_6|grn_data[12]          ; 1       ;
; led_latcha:comb_6|grn_data[13]          ; 1       ;
; led_latcha:comb_6|grn_data[14]          ; 1       ;
; led_latcha:comb_6|grn_data[15]          ; 1       ;
; Total number of inverted registers = 32 ;         ;
+-----------------------------------------+---------+


+---------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: tim:comb_4|lpm_counter:a_rtl_0 ;
+------------------------+-------------------+------------------------------------+
; Parameter Name         ; Value             ; Type                               ;
+------------------------+-------------------+------------------------------------+
; AUTO_CARRY_CHAINS      ; ON                ; AUTO_CARRY                         ;
; IGNORE_CARRY_BUFFERS   ; OFF               ; IGNORE_CARRY                       ;
; AUTO_CASCADE_CHAINS    ; ON                ; AUTO_CASCADE                       ;
; IGNORE_CASCADE_BUFFERS ; OFF               ; IGNORE_CASCADE                     ;
; LPM_WIDTH              ; 9                 ; Untyped                            ;
; LPM_DIRECTION          ; UP                ; Untyped                            ;
; LPM_MODULUS            ; 0                 ; Untyped                            ;
; LPM_AVALUE             ; UNUSED            ; Untyped                            ;
; LPM_SVALUE             ; UNUSED            ; Untyped                            ;
; LPM_PORT_UPDOWN        ; PORT_CONNECTIVITY ; Untyped                            ;
; DEVICE_FAMILY          ; FLEX10K           ; Untyped                            ;
; CARRY_CHAIN            ; MANUAL            ; Untyped                            ;
; CARRY_CHAIN_LENGTH     ; 48                ; CARRY_CHAIN_LENGTH                 ;
; NOT_GATE_PUSH_BACK     ; ON                ; NOT_GATE_PUSH_BACK                 ;
; CARRY_CNT_EN           ; SMART             ; Untyped                            ;
; LABWIDE_SCLR           ; ON                ; Untyped                            ;
; USE_NEW_VERSION        ; TRUE              ; Untyped                            ;
; CBXI_PARAMETER         ; NOTHING           ; Untyped                            ;
+------------------------+-------------------+------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.0 Build 33 02/05/2007 SJ Web Edition
    Info: Processing started: Thu Apr 09 17:08:59 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off xianshi -c xianshi
Info: Found 1 design units, including 1 entities, in source file xianshi.v
    Info: Found entity 1: xianshi
Info: Found 1 design units, including 1 entities, in source file led_latcha.v
    Info: Found entity 1: led_latcha
Info: Found 1 design units, including 1 entities, in source file dc.v
    Info: Found entity 1: dc
Info: Found 1 design units, including 1 entities, in source file drive.v
    Info: Found entity 1: drive
Info: Found 1 design units, including 1 entities, in source file tim.v
    Info: Found entity 1: tim
Critical Warning (10846): Verilog HDL Instantiation warning at xianshi.v(8): instance has no name
Critical Warning (10846): Verilog HDL Instantiation warning at drive.v(7): instance has no name
Critical Warning (10846): Verilog HDL Instantiation warning at xianshi.v(9): instance has no name
Critical Warning (10846): Verilog HDL Instantiation warning at xianshi.v(10): instance has no name
Info: Elaborating entity "xianshi" for the top level hierarchy
Info: Elaborating entity "tim" for hierarchy "tim:comb_4"
Info: Elaborating entity "drive" for hierarchy "drive:comb_5"
Info: Elaborating entity "dc" for hierarchy "drive:comb_5|dc:comb_4"
Info: Elaborating entity "led_latcha" for hierarchy "led_latcha:comb_6"
Info: Inferred 1 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=9) from the following logic: "tim:comb_4|a[0]~0"
Info: Found 1 design units, including 1 entities, in source file c:/altera/70/quartus/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Elaborated megafunction instantiation "tim:comb_4|lpm_counter:a_rtl_0"
Info: Found 1 design units, including 1 entities, in source file c:/altera/70/quartus/libraries/megafunctions/alt_counter_f10ke.tdf
    Info: Found entity 1: alt_counter_f10ke
Info: Elaborated megafunction instantiation "tim:comb_4|lpm_counter:a_rtl_0|alt_counter_f10ke:wysi_counter", which is child of megafunction instantiation "tim:comb_4|lpm_counter:a_rtl_0"
Info: Instantiated megafunction "tim:comb_4|lpm_counter:a_rtl_0" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "9"
    Info: Parameter "LPM_DIRECTION" = "UP"
    Info: Parameter "LPM_TYPE" = "LPM_COUNTER"
Info: Registers with preset signals will power-up high
Info: Implemented 173 device resources after synthesis - the final resource count might be different
    Info: Implemented 25 input pins
    Info: Implemented 49 output pins
    Info: Implemented 99 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings
    Info: Allocated 124 megabytes of memory during processing
    Info: Processing ended: Thu Apr 09 17:09:01 2009
    Info: Elapsed time: 00:00:02


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