?? bsl_flash.asm
字號:
NOP 4
CMPEQ .L1X B5,A0,A1 ; |220|
[ A1] B .S2 L27 ; |220|
[ A1] CMPLTU .L2 B7,B8,B0 ; |224|
|| [!A1] LDB .D1T1 *A3,A0 ; |221|
NOP 4
; BRANCH OCCURS ; |220|
;*----------------------------------------------------------------------------*
;* SOFTWARE PIPELINE INFORMATION
;*
;* Loop source line : 220
;* Loop opening brace source line : 220
;* Loop closing brace source line : 222
;* Known Minimum Trip Count : 1
;* Known Max Trip Count Factor : 1
;* Loop Carried Dependency Bound(^) : 13
;* Unpartitioned Resource Bound : 2
;* Partitioned Resource Bound(*) : 2
;* Resource Partition:
;* A-side B-side
;* .L units 0 1
;* .S units 1 0
;* .D units 1 2*
;* .M units 0 0
;* .X cross paths 0 0
;* .T address paths 2* 1
;* Long read paths 1 0
;* Long write paths 0 0
;* Logical ops (.LS) 0 0 (.L or .S unit)
;* Addition ops (.LSD) 4 0 (.L or .S or .D unit)
;* Bound(.L .S .LS) 1 1
;* Bound(.L .S .D .LS .LSD) 2* 1
;*
;* Disqualified loop: Loop carried dependency bound too large
;*----------------------------------------------------------------------------*
L25:
STB .D2T1 A0,*+SP(4) ; |221|
LDB .D2T2 *+SP(4),B5 ; |222|
NOP 4
CMPEQ .L2 B5,B4,B0 ; |222|
[!B0] B .S1 L25 ; |222|
[!B0] LDB .D1T1 *A3,A0 ; |221|
NOP 4
; BRANCH OCCURS ; |222|
;** --------------------------------------------------------------------------*
L26:
CMPLTU .L2 B7,B8,B0 ; |224|
;** --------------------------------------------------------------------------*
L27:
[!B0] B .S1 L30 ; |224|
MVKL .S2 RL10,B3 ; |224|
MVKL .S2 _FLASH_erase,B5 ; |224|
MVKH .S2 RL10,B3 ; |224|
MVKH .S2 _FLASH_erase,B5 ; |224|
SUB .D2 B8,B7,B4
; BRANCH OCCURS ; |224|
;** --------------------------------------------------------------------------*
B .S2 B5 ; |224|
ADD .D1 3,A5,A4
NOP 4
RL10: ; CALL OCCURS ; |224|
B .S1 L32 ; |224|
LDW .D2T2 *+SP(20),B3 ; |229|
LDW .D2T2 *+SP(24),B10 ; |229|
MVKL .S1 0x1800004,A0 ; |228|
|| LDW .D2T1 *+SP(16),A12 ; |229|
MVKH .S1 0x1800004,A0 ; |228|
|| LDW .D2T1 *+SP(12),A11 ; |229|
STW .D1T1 A10,*A0 ; |228|
|| LDW .D2T2 *+SP(28),B11 ; |229|
; BRANCH OCCURS ; |224|
;** --------------------------------------------------------------------------*
L28:
STB .D1T1 A0,*A8 ; |85|
STB .D1T2 B5,*A7 ; |86|
STB .D2T2 B11,*B1 ; |87|
STB .D1T1 A3,*A5 ; |196|
STB .D1T1 A0,*A9 ; |91|
STB .D2T2 B5,*B0 ; |92|
STB .D2T2 B12,*B2 ; |93|
STB .D1T1 A0,*A11 ; |94|
STB .D2T2 B5,*B9 ; |95|
STB .D1T1 A12,*A2 ; |96|
LDB .D1T1 *A5,A0 ; |201|
NOP 4
STB .D2T1 A0,*+SP(4) ; |201|
LDB .D2T2 *+SP(4),B4 ; |202|
NOP 4
CMPEQ .L2 B4,-1,B0 ; |202|
[ B0] B .S1 L32 ; |202|
[ B0] LDW .D2T2 *+SP(20),B3 ; |229|
[ B0] LDW .D2T2 *+SP(24),B10 ; |229|
[ B0] LDW .D2T1 *+SP(16),A12 ; |229|
|| [ B0] MVKL .S1 0x1800004,A0 ; |228|
[ B0] LDW .D2T1 *+SP(12),A11 ; |229|
|| [ B0] MVKH .S1 0x1800004,A0 ; |228|
[ B0] STW .D1T1 A10,*A0 ; |228|
|| [ B0] LDW .D2T2 *+SP(28),B11 ; |229|
; BRANCH OCCURS ; |202|
;** --------------------------------------------------------------------------*
LDB .D1T1 *A5,A0 ; |203|
;*----------------------------------------------------------------------------*
;* SOFTWARE PIPELINE INFORMATION
;*
;* Loop source line : 202
;* Loop opening brace source line : 202
;* Loop closing brace source line : 204
;* Known Minimum Trip Count : 1
;* Known Max Trip Count Factor : 1
;* Loop Carried Dependency Bound(^) : 13
;* Unpartitioned Resource Bound : 2
;* Partitioned Resource Bound(*) : 2
;* Resource Partition:
;* A-side B-side
;* .L units 0 1
;* .S units 1 0
;* .D units 1 2*
;* .M units 0 0
;* .X cross paths 0 0
;* .T address paths 2* 1
;* Long read paths 1 0
;* Long write paths 0 0
;* Logical ops (.LS) 0 0 (.L or .S unit)
;* Addition ops (.LSD) 4 0 (.L or .S or .D unit)
;* Bound(.L .S .LS) 1 1
;* Bound(.L .S .D .LS .LSD) 2* 1
;*
;* Disqualified loop: Loop carried dependency bound too large
;*----------------------------------------------------------------------------*
L29:
NOP 4
STB .D2T1 A0,*+SP(4) ; |203|
LDB .D2T2 *+SP(4),B4 ; |204|
NOP 4
CMPEQ .L2 B4,-1,B0 ; |204|
[!B0] B .S1 L29 ; |204|
[!B0] LDB .D1T1 *A5,A0 ; |203|
NOP 4
; BRANCH OCCURS ; |204|
;** --------------------------------------------------------------------------*
L30:
LDW .D2T2 *+SP(20),B3 ; |229|
;** --------------------------------------------------------------------------*
L31:
LDW .D2T2 *+SP(24),B10 ; |229|
LDW .D2T1 *+SP(16),A12 ; |229|
|| MVKL .S1 0x1800004,A0 ; |228|
LDW .D2T1 *+SP(12),A11 ; |229|
|| MVKH .S1 0x1800004,A0 ; |228|
STW .D1T1 A10,*A0 ; |228|
|| LDW .D2T2 *+SP(28),B11 ; |229|
;** --------------------------------------------------------------------------*
L32:
B .S2 B3 ; |229|
|| LDW .D2T1 *+SP(8),A10 ; |229|
LDW .D2T2 *++SP(32),B12 ; |229|
NOP 4
; BRANCH OCCURS ; |229|
.sect ".text:_FLASH_checksum"
.clink
.global _FLASH_checksum
;******************************************************************************
;* FUNCTION NAME: _FLASH_checksum *
;* *
;* Regs Modified : A0,A1,A2,A3,A4,A5,A6,A7,B0,B1,B3,B4,B5,B6,B9 *
;* Regs Used : A0,A1,A2,A3,A4,A5,A6,A7,B0,B1,B3,B4,B5,B6,B9 *
;* Local Frame Size : 0 Args + 0 Auto + 0 Save = 0 byte *
;******************************************************************************
_FLASH_checksum:
;** --------------------------------------------------------------------------*
MVKL .S1 0x1800004,A0 ; |131|
MVKH .S1 0x1800004,A0 ; |131|
|| MVKL .S2 _validate_FLASH,B6 ; |144|
LDW .D1T1 *A0,A6 ; |131|
|| MVKH .S2 _validate_FLASH,B6 ; |144|
B .S2 B6 ; |144|
MVKL .S2 0x1800004,B5 ; |139|
MV .D2 B3,B9 ; |129|
MVKL .S2 RL12,B3 ; |144|
CLR .S1 A6,4,7,A0 ; |139|
|| MVKH .S2 0x1800004,B5 ; |139|
STW .D2T1 A0,*B5 ; |139|
|| MVKH .S2 RL12,B3 ; |144|
|| MV .D1 A4,A7
|| MV .S1X B4,A2
RL12: ; CALL OCCURS ; |144|
MV .D1 A4,A1 ; |144|
[!A1] B .S1 L36 ; |144|
ZERO .D1 A0 ; |145|
[!A1] MVK .S1 0xffffffff,A0 ; |143|
NOP 3
; BRANCH OCCURS ; |144|
;** --------------------------------------------------------------------------*
[!A2] B .S1 L36 ; |146|
MV .S2X A2,B4 ; |147|
NOP 4
; BRANCH OCCURS ; |146|
;** --------------------------------------------------------------------------*
MVK .S2 0x4,B1 ; init prolog collapse predicate
;*----------------------------------------------------------------------------*
;* SOFTWARE PIPELINE INFORMATION
;*
;* Loop source line : 146
;* Loop opening brace source line : 146
;* Loop closing brace source line : 148
;* Known Minimum Trip Count : 1
;* Known Max Trip Count Factor : 1
;* Loop Carried Dependency Bound(^) : 0
;* Unpartitioned Resource Bound : 1
;* Partitioned Resource Bound(*) : 1
;* Resource Partition:
;* A-side B-side
;* .L units 0 0
;* .S units 0 1*
;* .D units 1* 0
;* .M units 0 0
;* .X cross paths 0 0
;* .T address paths 1* 0
;* Long read paths 0 0
;* Long write paths 0 0
;* Logical ops (.LS) 0 0 (.L or .S unit)
;* Addition ops (.LSD) 1 1 (.L or .S or .D unit)
;* Bound(.L .S .LS) 0 1*
;* Bound(.L .S .D .LS .LSD) 1* 1*
;*
;* Searching for software pipeline schedule at ...
;* ii = 1 Schedule found with 7 iterations in parallel
;* done
;*
;* Collapsed epilog stages : 6
;* Prolog not entirely removed
;* Collapsed prolog stages : 4
;*
;* Minimum required memory pad : 0 bytes
;*
;* For further improvement on this loop, try option -mh5
;*
;* Minimum safe trip count : 1
;*----------------------------------------------------------------------------*
L33: ; PIPED LOOP PROLOG
B .S2 L34 ; (P) |148|
B .S2 L34 ; (P) @|148|
B .S2 L34 ; (P) @@|148|
SUB .D2 B4,1,B0
|| MV .D1 A7,A3
|| B .S2 L34 ; (P) @@@|148|
SUB .S1X B4,1,A1
|| LDBU .D1T1 *A3++,A4 ; (P) |147|
|| [ B0] SUB .D2 B0,1,B0 ; (P) @@@@@|148|
|| [ B0] B .S2 L34 ; (P) @@@@|148|
;** --------------------------------------------------------------------------*
L34: ; PIPED LOOP KERNEL
[ B1] SUB .D2 B1,1,B1 ;
|| [ A1] SUB .S1 A1,1,A1 ;
|| [!B1] ADD .L1 A4,A0,A0 ; |147|
|| [ A1] LDBU .D1T1 *A3++,A4 ; @@@@@|147|
|| [ B0] B .S2 L34 ; @@@@@|148|
|| [ B0] SUB .L2 B0,1,B0 ; @@@@@@|148|
;** --------------------------------------------------------------------------*
L35: ; PIPED LOOP EPILOG
;** --------------------------------------------------------------------------*
;** --------------------------------------------------------------------------*
L36:
B .S2 B9 ; |155|
MVKL .S1 0x1800004,A3 ; |151|
MVKH .S1 0x1800004,A3 ; |151|
STW .D1T1 A6,*A3 ; |151|
MV .S1 A0,A4 ; |154|
NOP 1
; BRANCH OCCURS ; |155|
;******************************************************************************
;* UNDEFINED EXTERNAL REFERENCES *
;******************************************************************************
.global __BOARD_init
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