/*****************************************************************************
**                                                                          **
**  Name:   ezkitBF5xx_initcode EXAMPLE                                     **
**                                                                          **
******************************************************************************

(C) Copyright 2007 - Analog Devices, Inc.  All rights reserved.

Project Name:   ezkitBF5xx_initcode

Version:        v3.0

Last Modified:  05/06/08 ap-muc

History:        v0.0 05/22/07 ap-muc

Tested
Software:       VisualDSP++ 4.5.5.0 (Updated June 2007)

Supported
Software:       VisualDSP++ 4.5.0.0

Tested
Hardware:       ADSP-BF533 EZ-KIT Lite Rev. 1.7 Silicon Rev. 0.4
                ADSP-BF533 EZ-KIT Lite Rev. 2.1 Silicon Rev. 0.5
                ADSP-BF537 EZ-KIT Lite Rev. 1.3 Silicon Rev. 0.2
                ADSP-BF538 EZ-KIT Lite Rev. 1.2 Silicon Rev. 0.3
                ADSP-BF561 EZ-KIT Lite Rev. 1.3 Silicon Rev. 0.3
                ADSP-BF561 EZ-KIT Lite Rev. 2.1 Silicon Rev. 0.5

Supported
Plattforms:     ADSP-BF533 EZ-KIT Lite Rev 1.7 and above
                ADSP-BF533 EZ-KIT Lite Rev 1.6 and below (modifications required, only 32MB SDRAM installed)
                ADSP-BF537 EZ-KIT Lite
                ADSP-BF538 EZ-KIT Lite
                ADSP-BF561 EZ-KIT Lite Silicon Rev. 0.2 and above

Connections:    ADDS-HPUSB-ICE

Project
Properties:     Assemble : Additional include directories -> ..\ADSP-BF5xx EZ-KIT Lite\;$(VDSP)\Blackfin\lib\src\libdsp\;..\src\;..\src\bksyscontrol\
                Link : LDF Preprocessing : Additional include directories -> ..\src\

Hardware
Settings:       default

Purpose:        General Initialization example for ADSP-BF5xx EZ-KIT Lite
                Included are:
                - PLL Settings (optimized for high sclk speed)
                - Voltage Regulator Settings
                - EBIU settings for the EZ-KIT Lite (Asynchronous and SDR/DDR SDRAM memory)
                - Bit Rate handler for Mode 'Boot from UART host (slave mode)' (ADSP-BF537 EZ-KIT Lite only)

Restrictions:   - Waits states for async flash interface are not optimized yet. Default/Save settings are still included
                - For ADSP-BF561 EZ-KIT Lite: Wait states for async flash interface are not optimized yet. Default/Save settings are still included

Hint for
ADSP-BF561:     Init code is supported beginning with the November update of VisualDSP++
                Please read EE-314: Booting the ADSP-BF561 Blackfin Processor.
                Required Loader Switches (Project Options->Load->Options->Addtidional Options): -NoFinalTag, -nosecondstagekernel
                For changing PLL settings it is absolutly necessary, that Core B is in idle mode !!!
                The programmer has to take care of this !!!
                This init code assumes that Core B is in idle state (as it is immediately after booting) !!!
*****************************************************************************/

/*****************************************************************************
 Include / Import Files
******************************************************************************/

#include "macros.h"
#include "system.h"

#if defined __ADSPBF537__
    #include "UART.h"
#endif

/****************************************************************************
 Main Program
*****************************************************************************/

.GLOBAL _initcode;

.SECTION L1_code;

_initcode:


/*****************************************************************************
 Pre-Init Section
 Save all used register on the stack
******************************************************************************/

link 0;
[--SP] = ASTAT;
[--SP] = (R7:0,P5:0);
IMM32(P5,SYS_MMR_BASE);


/************************************************
* System Interrupt Wakeup Registers (SIC_IWRx)  *
* Required for PLL_CTL and VR_CTL configuration *
* Processor idle and wake up after PLL_LOCKCNT  *
* expired.Reset = 0xFFFF FFFF                   *
* disable all other interrupt sources in the    *
* meantime to disable unwanted wake up events   *
************************************************/

R7 = IWR_DISABLE_ALL;

#if defined (__ADSPBF538__) || defined (__ADSPBF561__)
    [P5 + lo(SIC_IWR1)] = R7;
#endif

R7 = IRQ_PLL_WAKEUP;
[P5 + lo(SIC_IWR0)] = R7;


#if defined __ADSPBF537__

/*************************************************
 Test for Boot Modes that reuqire special actions
*************************************************/

R7 = w[P5 + lo(SYSCR)] (z);
R6 = BMODE (z);
R7 = R6 & R7;


/****************************************
 Mode 'Boot from UART host (slave mode)'
 Save current BIT RATE value
****************************************/

R6 = BMODE_UART0HOST (z);
CC = R6 == R7;
if !CC jump DPM;
call __uart0_save_bitrate;

#endif


DPM: nop;
/*****************************************************************************************
 Description:   Dynamic Power Managment with The System Control ROM Function 
*****************************************************************************************/

call __full_on;


#if defined __ADSPBF537__

/*************************************************
 Test for Boot Modes that reuqire special actions
*************************************************/

R7 = w[P5 + lo(SYSCR)] (z);
R6 = BMODE (z);
R7 = R6 & R7;


/*******************************************************
 Mode 'Boot from UART host (slave mode)'
 Update UART Divisor latch register UART_DLH & UART_DLL
 accroding to new system clock frequency
*******************************************************/

R6 = BMODE_UART0HOST (z);
CC = R6 == R7;
if !CC jump EBIU;
call __uart0_set_bitrate;

#endif


EBIU: nop;
/*****************************************************************************
 Description:   Configure EBIU
******************************************************************************/


/*****************************************************************************
 Description:   Configure and enable asynchronous memory
******************************************************************************/


/**********************************************
* Asynchronous Memory Bank Control 0 Register *
**********************************************/

IMM32(R7,EBIU_AMBCTL0_VAL);
[P5 + lo(EBIU_AMBCTL0)] = R7;


/**********************************************
* Asynchronous Memory Bank Control 1 Register *
**********************************************/

IMM32(R7,EBIU_AMBCTL1_VAL);
[P5 + lo(EBIU_AMBCTL1)] = R7;


/**********************************************
* Asynchronous Memory Global Control Register *
***********************************************/

R7.L = EBIU_AMGCTL_VAL;
w[P5 + lo(EBIU_AMGCTL)] = R7;


SDRSDRAM:

/*****************************************************************************
 Description:   Configure and enable SDRAM
******************************************************************************/

#if defined WORKAROUND_05000070 /* see 'ezkitBF533_initcode.asm' for more details */
    R7.L = w[P5 + lo(EBIU_SDSTAT)];
    CC = bittst(R7, bitpos(SDRS));
    if !CC jump skip_sdram_enable;
#endif


/*************************************
* SDRAM Memory Bank Control Register *
**************************************/

#if defined __ADSPBF561__
    IMM32(R7,EBIU_SDBCTL_VAL);
    [P5 + lo(EBIU_SDBCTL)] = R7;
#else
    R7.L = EBIU_SDBCTL_VAL;
    w[P5 + lo(EBIU_SDBCTL)] = R7;
#endif


/***************************************
* SDRAM Memory Global Control Register *
***************************************/

IMM32(R7,EBIU_SDGCTL_VAL);
[P5 + lo(EBIU_SDGCTL)] = R7;


/***************************************************************************
* SDRAM Refresh Rate Control Register                                      *
* RDIV has always to be re-calculated according to the actual system clock *
* You can either use the defined value that fits to the PCC settings or    *
* call get_rdiv to calculate RDIV 'on the fly'                            *
***************************************************************************/

call __get_rdiv;
w[P5 + lo(EBIU_SDRRC)] = R0;


/*********************************************
* Restore System Interrupt Wakeup Registers  *
*********************************************/

R7 = IWR_ENABLE_ALL;

#if defined (__ADSPBF538__) || defined (__ADSPBF561__)
    [P5 + lo(SIC_IWR1)] = R7;
#endif


/*****************************************************************************
 Post-Init Section
 Restore all saved registers from stack
******************************************************************************/

(R7:0,P5:0) = [SP++];
ASTAT = [SP++];
unlink;
rts;

_initcode.end:


/****************************************************************************
 EOF
*****************************************************************************/