architecture rtl of test_state is
  type   state_type is (s0, s1, s2, s3);
  signal state, next_state : state_type;
begin  --  rtl 

  state_encode : process ( state, con1, con2, con3 )
  begin
    next_state <= s1;  -- Note:  This line will optomize your state machine
    -- in synthesis.  It does nothing in simulation.
    case state is
      when s0 =>
        next_state <= s1;
      when s1 =>
        if ( con1 = '1' ) then
          next_state <= s2;
        else
          next_state <= s1;
        end if;
      when s2 =>
        next_state <= s3;
      when s3 =>
        if ( con2 = '0' ) then
          next_state <= s3;
        elsif ( con3 = '0' ) then
          next_state <= s2;
        else
          next_state <= s0;
        end if;
    end case;
  end process state_encode;

  state_register : process ( reset, clk )
  begin
    if ( reset = '0' ) then
      state <= s0;
    elsif ( clk'event and clk = '1' ) then
      state <= next_state;
    end if;
  end process state_register;

  state_decode : process ( state, con1, con2, con3 )
  begin
    case state is
      when s0 =>
        out1 <= '0';
        out2 <= '0';
      when s1 =>
        out1 <= '1';
        out2 <= '0';
      when s2 =>
        out1 <= '0';
        out2 <= '1';
      when s3 =>
        if ( con2 = '0' ) then
          out1 <= '0';
          out2 <= '0';
        elsif ( con3 = '0' ) then
          out1 <= '0';
          out2 <= '1';
        else
          out1 <= '1';
          out2 <= '1';
        end if;
    end case;
  end process state_decode;

end rtl;