+			base += 64 << 10;+			++i;+		}+	} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) ||+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) ||+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) {+		/* set sector offsets for top boot block type		*/+		base += info->size;+		i = info->sector_count;+		for (n=0; n<8; ++n) {		/*  8 x 8k boot sectors	*/+			base -= 8 << 10;+			--i;+			info->start[i] = base;+		}+		while (i > 0) {			/* 64k regular sectors	*/+			base -= 64 << 10;+			--i;+			info->start[i] = base;+		}+	} else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) {+		/* set sector offsets for top boot block type		*/+		base += info->size;+		i = info->sector_count;+		/*  1 x 16k boot sector */+		base -= 16 << 10;+		--i;+		info->start[i] = base;+		/*  2 x 8k  boot sectors */+		for (n=0; n<2; ++n) {+			base -= 8 << 10;+			--i;+			info->start[i] = base;+		}+		/*  1 x 32k boot sector */+		base -= 32 << 10;+		--i;+		info->start[i] = base;++		while (i > 0) {			/* 64k regular sectors	*/+			base -= 64 << 10;+			--i;+			info->start[i] = base;+		}+	} else {+	    if (info->flash_id & FLASH_BTYPE) {+		/* set sector offsets for bottom boot block type	*/+		info->start[0] = base + 0x00000000;+		info->start[1] = base + 0x00004000;+		info->start[2] = base + 0x00006000;+		info->start[3] = base + 0x00008000;+		for (i = 4; i < info->sector_count; i++) {+			info->start[i] = base + (i * 0x00010000) - 0x00030000;+		}+	    } else {+		/* set sector offsets for top boot block type		*/+		i = info->sector_count - 1;+		info->start[i--] = base + info->size - 0x00004000;+		info->start[i--] = base + info->size - 0x00006000;+		info->start[i--] = base + info->size - 0x00008000;+		for (; i >= 0; i--) {+			info->start[i] = base + i * 0x00010000;+		}+	    }+	}++	/* check for protected sectors */+	for (i = 0; i < info->sector_count; i++) {+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */+		/* D0 = 1 if protected */+		addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]);+		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)+		  info->protect[i] = 0;+		else+		  info->protect[i] = addr2[CFG_FLASH_READ2] & 1;+	}++	/*+	 * Prevent writes to uninitialized FLASH.+	 */+	if (info->flash_id != FLASH_UNKNOWN) {+		addr2 = (CFG_FLASH_WORD_SIZE *)info->start[0];+		*addr2 = (CFG_FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */+	}++	return (info->size);+}+++/*-----------------------------------------------------------------------+ */++int	flash_erase (flash_info_t *info, int s_first, int s_last)+{+	volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *)(info->start[0]);+	volatile CFG_FLASH_WORD_SIZE *addr2;+	int flag, prot, sect, l_sect;+	ulong start, now, last;+	int i;++	if ((s_first < 0) || (s_first > s_last)) {+		if (info->flash_id == FLASH_UNKNOWN) {+			printf ("- missing\n");+		} else {+			printf ("- no sectors to erase\n");+		}+		return 1;+	}++	if (info->flash_id == FLASH_UNKNOWN) {+		printf ("Can't erase unknown flash type - aborted\n");+		return 1;+	}++	prot = 0;+	for (sect=s_first; sect<=s_last; ++sect) {+		if (info->protect[sect]) {+			prot++;+		}+	}++	if (prot) {+		printf ("- Warning: %d protected sectors will not be erased!\n",+			prot);+	} else {+		printf ("\n");+	}++	l_sect = -1;++	/* Disable interrupts which might cause a timeout here */+	flag = disable_interrupts();++	/* Start erase on unprotected sectors */+	for (sect = s_first; sect<=s_last; sect++) {+		if (info->protect[sect] == 0) {	/* not protected */+		    addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[sect]);+		    if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {+			addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;+			addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;+			addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080;+			addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;+			addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;+			addr2[0] = (CFG_FLASH_WORD_SIZE)0x00500050;  /* block erase */+			for (i=0; i<50; i++)+			  udelay(1000);  /* wait 1 ms */+		    } else {+			if (sect == s_first) {+			    addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;+			    addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;+			    addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080;+			    addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;+			    addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;+			}+			addr2[0] = (CFG_FLASH_WORD_SIZE)0x00300030;  /* sector erase */+		    }+		    l_sect = sect;+		}+	}++	/* re-enable interrupts if necessary */+	if (flag)+		enable_interrupts();++	/* wait at least 80us - let's wait 1 ms */+	udelay (1000);++	/*+	 * We wait for the last triggered sector+	 */+	if (l_sect < 0)+		goto DONE;++	start = get_timer (0);+	last  = start;+	addr = (CFG_FLASH_WORD_SIZE *)(info->start[l_sect]);+	while ((addr[0] & (CFG_FLASH_WORD_SIZE)0x00800080) != (CFG_FLASH_WORD_SIZE)0x00800080) {+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {+			printf ("Timeout\n");+			return 1;+		}+		/* show that we're waiting */+		if ((now - last) > 1000) {	/* every second */+			putc ('.');+			last = now;+		}+	}++DONE:+	/* reset to read mode */+	addr = (CFG_FLASH_WORD_SIZE *)info->start[0];+	addr[0] = (CFG_FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */++	printf (" done\n");+	return 0;+}++/*-----------------------------------------------------------------------+ * Copy memory to flash, returns:+ * 0 - OK+ * 1 - write timeout+ * 2 - Flash not erased+ */++int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)+{+	ulong cp, wp, data;+	int i, l, rc;++	wp = (addr & ~3);	/* get lower word aligned address */++	/*+	 * handle unaligned start bytes+	 */+	if ((l = addr - wp) != 0) {+		data = 0;+		for (i=0, cp=wp; i<l; ++i, ++cp) {+#ifdef CONFIG_LPC+			data = data | ((*(uchar *)cp)<<(8*i));+#else+			data = (data << 8) | (*(uchar *)cp);+#endif+		}+		for (; i<4 && cnt>0; ++i) {+#ifdef CONFIG_LPC+			data = data  | ((*src++)<<(8*i));+#else+			data = (data << 8) | *src++;+#endif+			--cnt;+			++cp;+		}+		for (; cnt==0 && i<4; ++i, ++cp) {+#ifdef CONFIG_LPC+			data = data | ((*(uchar *)cp)<<(8*i));+#else+			data = (data << 8) | (*(uchar *)cp);+#endif+		}++		if ((rc = write_word(info, wp, data)) != 0) {+			return (rc);+		}+		wp += 4;+	}++	/*+	 * handle word aligned part+	 */+	while (cnt >= 4) {+		data = 0;+#ifdef CONFIG_LPC+		data = (*(ulong*)src);+		src += 4;+#else+		for (i=0; i<4; ++i) {+			data = (data << 8) | *src++;+		}+#endif+		if ((rc = write_word(info, wp, data)) != 0) {+			return (rc);+		}+		wp  += 4;+		cnt -= 4;+	}++	if (cnt == 0) {+		return (0);+	}++	/*+	 * handle unaligned tail bytes+	 */+	data = 0;+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {+#ifdef CONFIG_LPC+		data = data  | ((*src++)<<(8*i));+#else+		data = (data << 8) | *src++;+#endif+		--cnt;+	}+	for (; i<4; ++i, ++cp) {+#ifdef CONFIG_LPC+		data = data | ((*(uchar *)cp)<<(8*i));+#else+		data = (data << 8) | (*(uchar *)cp);+#endif+	}++	return (write_word(info, wp, data));+}++/*-----------------------------------------------------------------------+ * Write a word to Flash, returns:+ * 0 - OK+ * 1 - write timeout+ * 2 - Flash not erased+ */+static int write_word (flash_info_t *info, ulong dest, ulong data)+{+	volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[0]);+	volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *)dest;+	volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *)&data;+	ulong start;+	int flag;+	int i;++	/* Check if Flash is (sufficiently) erased */+	if ((*((volatile ulong *)dest) & data) != data) {+		return (2);+	}+	/* Disable interrupts which might cause a timeout here */+	flag = disable_interrupts();++	for (i=0; i<4/sizeof(CFG_FLASH_WORD_SIZE); i++)+	  {+	    addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;+	    addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;+	    addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00A000A0;++	    dest2[i] = data2[i];++	    /* re-enable interrupts if necessary */+	    if (flag)+	      enable_interrupts();++	    /* data polling for D7 */+	    start = get_timer (0);+	    while ((dest2[i] & (CFG_FLASH_WORD_SIZE)0x00800080) !=+		   (data2[i] & (CFG_FLASH_WORD_SIZE)0x00800080)) {+	      if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {+		return (1);+	      }+	    }+	  }++	return (0);+}++/*-----------------------------------------------------------------------+ */diff -Naur u-boot-origin/board/lpc2294/lowlevel_init.S u-boot-1.1.3/board/lpc2294/lowlevel_init.S--- u-boot-origin/board/lpc2294/lowlevel_init.S	1970-01-01 07:00:00.000000000 +0700+++ u-boot-1.1.3/board/lpc2294/lowlevel_init.S	2005-09-07 10:16:32.000000000 +0800@@ -0,0 +1,184 @@+/*+ * (C) Copyright 2004+ * DAVE Srl+ *+ * http://www.dave-tech.it+ * http://www.wawnet.biz+ * mailto:info@wawnet.biz+ *+ * memsetup-sa1110.S (blob): memory setup for various SA1110 architectures+ * Modified By MATTO+ *+ * Copyright (C) 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl)+ *+ * This program is free software; you can redistribute it and/or modify+ * it under the terms of the GNU General Public License as published by+ * the Free Software Foundation; either version 2 of the License, or+ * (at your option) any later version.+ *+ * This program is distributed in the hope that it will be useful,+ * but WITHOUT ANY WARRANTY; without even the implied warranty of+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the+ * GNU General Public License for more details.+ *+ * You should have received a copy of the GNU General Public License+ * along with this program; if not, write to the Free Software+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA+ *+ */++/*+ * Documentation:+ * Intel Corporation, "Intel StrongARM SA-1110 Microprocessor+ *     Advanced Developer's manual, December 1999+ *+ * Intel has a very hard to find SDRAM configurator on their web site:+ *   http://appzone.intel.com/hcd/sa1110/memory/index.asp+ *+ * NOTE: This code assumes that an SA1110 CPU *always* uses SDRAM. This+ * appears to be true, but it might be possible that somebody designs a+ * board with mixed EDODRAM/SDRAM memory (which is a bad idea). -- Erik+ *+ * 04-10-2001:  SELETZ+ * - separated memory config for multiple platform support+ * - perform SA1110 Hardware Reset Procedure+ *+ */++.equ    B0_Tacs,      0x0 /* 0clk */+.equ    B0_Tcos,      0x0 /* 0clk */+.equ    B0_Tacc,      0x4 /* 6clk */+.equ    B0_Tcoh,      0x0 /* 0clk */+.equ    B0_Tah,       0x0 /* 0clk */+.equ    B0_Tacp,      0x0 /* 0clk */+.equ    B0_PMC,       0x0 /* normal(1data) */+/* Bank 1 parameter */+.equ    B1_Tacs,      0x3 /* 4clk */+.equ    B1_Tcos,      0x3 /* 4clk */+.equ    B1_Tacc,      0x7 /* 14clkv */+.equ    B1_Tcoh,      0x3 /* 4clk */+.equ    B1_Tah,       0x3 /* 4clk */+.equ    B1_Tacp,      0x3 /* 6clk */+.equ    B1_PMC,       0x0 /* normal(1data) */++/* Bank 2 parameter - LAN91C96 */+.equ    B2_Tacs,      0x3 /* 4clk */+.equ    B2_Tcos,      0x3 /* 4clk */+.equ    B2_Tacc,      0x7 /* 14clk */+.equ    B2_Tcoh,      0x3 /* 4clk */+.equ    B2_Tah,       0x3 /* 4clk */+.equ    B2_Tacp,      0x3 /* 6clk */+.equ    B2_PMC,       0x0 /* normal(1data) */++/* Bank 3 parameter */+.equ    B3_Tacs,      0x3 /* 4clk */+.equ    B3_Tcos,      0x3 /* 4clk */+.equ    B3_Tacc,      0x7 /* 14clk */+.equ    B3_Tcoh,      0x3 /* 4clk */+.equ    B3_Tah,       0x3 /* 4clk */+.equ    B3_Tacp,      0x3 /* 6clk */+.equ    B3_PMC,       0x0 /* normal(1data) */++/* Bank 4 parameter */+.equ    B4_Tacs,      0x3 /* 4clk */+.equ    B4_Tcos,      0x3 /* 4clk */+.equ    B4_Tacc,      0x7 /* 14clk */+.equ    B4_Tcoh,      0x3 /* 4clk */+.equ    B4_Tah,       0x3 /* 4clk */+.equ    B4_Tacp,      0x3 /* 6clk */+.equ    B4_PMC,       0x0 /* normal(1data) */++/* Bank 5 parameter */+.equ    B5_Tacs,      0x3 /* 4clk */+.equ    B5_Tcos,      0x3 /* 4clk */+.equ    B5_Tacc,      0x7 /* 14clk */+.equ    B5_Tcoh,      0x3 /* 4clk */+.equ    B5_Tah,       0x3 /* 4clk */+.equ    B5_Tacp,      0x3 /* 6clk */+.equ    B5_PMC,       0x0 /* normal(1data) */++/* Bank 6(if SROM) parameter */+.equ    B6_Tacs,      0x3 /* 4clk */+.equ    B6_Tcos,      0x3 /* 4clk */+.equ    B6_Tacc,      0x7 /* 14clk */+.equ    B6_Tcoh,      0x3 /* 4clk */+.equ    B6_Tah,       0x3 /* 4clk */+.equ    B6_Tacp,      0x3 /* 6clk */+.equ    B6_PMC,       0x0 /* normal(1data) */++/* Bank 7(if SROM) parameter */+.equ    B7_Tacs,      0x3 /* 4clk */+.equ    B7_Tcos,      0x3 /* 4clk */+.equ    B7_Tacc,      0x7 /* 14clk */+.equ    B7_Tcoh,      0x3 /* 4clk */+.equ    B7_Tah,       0x3 /* 4clk */+.equ    B7_Tacp,      0x3 /* 6clk */+.equ    B7_PMC,       0x0 /* normal(1data) */++/* Bank 6 parameter */+.equ    B6_MT,        0x3 /* SDRAM */+.equ    B6_Trcd,      0x0 /* 2clk */