+_start:	ldr     pc, ResetAddr++        ldr     pc, UndefinedAddr+        ldr     pc, SWI_Addr+        ldr     pc, PrefetchAddr+        ldr     pc, DataAbortAddr+        ldr     pc, Nouse+        LDR     pc, IRQ_Addr+        LDR     pc, FIQ_Addr+        +ResetAddr:+  .word 0x80000050+UndefinedAddr:+	.word	0x81000004+SWI_Addr:+	.word	0x81000008+PrefetchAddr:+	.word 0x8100000c+DataAbortAddr:+	.word 0x81000010+Nouse:+	.word 0x8100001c+IRQ_Addr:+	.word 0x81000018+FIQ_Addr:+	.word 0x8100001c++/*+ *************************************************************************+ *+ * Startup Code (reset vector)+ *+ * do important init only if we don't start from memory!+ * relocate u-boot to ram+ * setup stack+ * jump to second stage+ *+ *************************************************************************+ */++_TEXT_BASE:+	.word	TEXT_BASE++.globl _armboot_start+_armboot_start:+	.word _start++/*+ * These are defined in the board-specific linker script.+ */+.globl _bss_start+_bss_start:+	.word __bss_start++.globl _bss_end+_bss_end:+	.word _end++#ifdef CONFIG_USE_IRQ+/* IRQ stack memory (calculated at run-time) */+.globl IRQ_STACK_START+IRQ_STACK_START:+	.word	0x0badc0de++/* IRQ stack memory (calculated at run-time) */+.globl FIQ_STACK_START+FIQ_STACK_START:+	.word 0x0badc0de+#endif+++/*+ * the actual reset code+ */+#define PINSEL0 0xE002C000+#define PINSEL2 0xE002C014+#define BCFG0 0xFFE00000+#define BCFG1 0xFFE00004+#define BCFG2 0xFFE00008+#define BCFG3 0xFFE0000C++reset:+	/*+	 * set the cpu to SVC32 mode,disable all interrupts+	 */+	mrs	r0,cpsr+	bic	r0,r0,#0x3f+	orr	r0,r0,#0x13+	orr r0,r0,#0x80+	orr r0,r0,#0x40+	msr	cpsr,r0+	+	/*+	 *Initialize external bus controller, determined by target board+	 */+	ldr r0,=PINSEL0+	ldr r1,=0x80000005+	str r1,[r0]+	+  ldr r0,=PINSEL2+  ldr r1,=0x0f814924+  str r1,[r0]+  +  ldr r0,=BCFG0+  ldr r1,=0x2000ffef+  str r1,[r0]+  +  ldr r0,=BCFG1+  ldr r1,=0x2000ffef+  str r1,[r0]+  +  ldr r0,=BCFG2+  ldr r1,=0x10007c67+  str r1,[r0]+  +  ldr r0,=BCFG3+  ldr r1,=0x0000ffef+  str r1,[r0]+  ++	/*+	 * we do sys-critical inits only at reboot,+	 * not when booting from ram!+	 */++#ifndef CONFIG_SKIP_LOWLEVEL_INIT+	bl	cpu_init_crit+	/*+	 * before relocating, we have to setup RAM timing+	 * because memory timing is board-dependend, you will+	 * find a memsetup.S in your board directory.+	 */+	bl	lowlevel_init+#endif++#ifndef CONFIG_SKIP_RELOCATE_UBOOT+relocate:				/* relocate U-Boot to RAM	    */+	adr	r0, _start		/* r0 <- current position of code   */+	ldr	r1, _TEXT_BASE		/* test if we run from flash or RAM */+	cmp     r0, r1                  /* don't reloc during debug         */+	beq     stack_setup++	ldr	r2, _armboot_start+	ldr	r3, _bss_start+	sub	r2, r3, r2		/* r2 <- size of armboot            */+	add	r2, r0, r2		/* r2 <- source end address         */++copy_loop:+	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */+	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */+	cmp	r0, r2			/* until source end addreee [r2]    */+	ble	copy_loop++/*+	now copy to sram the interrupt vector+*/+	adr	r0, real_vectors+	add	r2, r0, #1024+	ldr	r1, =0x81000000+	add	r1, r1, #0x08+vector_copy_loop:+	ldmia	r0!, {r3-r10}+	stmia	r1!, {r3-r10}+	cmp	r0, r2+	ble	vector_copy_loop+#endif	/* CONFIG_SKIP_RELOCATE_UBOOT */++	/* Set up the stack						    */+stack_setup:+	ldr	r0, _TEXT_BASE		/* upper 128 KiB: relocated uboot   */+	sub	r0, r0, #CFG_MALLOC_LEN	/* malloc area                      */+	sub	r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo                        */+#ifdef CONFIG_USE_IRQ+	sub	r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)+#endif+	sub	sp, r0, #12		/* leave 3 words for abort-stack    */++	ldr	pc, _start_armboot++_start_armboot:	.word start_armboot+++/*+ *************************************************************************+ *+ * CPU_init_critical registers+ *+ * setup important registers+ * setup memory timing+ *+ *************************************************************************+ */+/*+#define INTCON (0x01c00000+0x200000)+#define INTMSK (0x01c00000+0x20000c)+#define LOCKTIME (0x01c00000+0x18000c)+#define PLLCON (0x01c00000+0x180000)+#define CLKCON (0x01c00000+0x180004)+#define WTCON (0x01c00000+0x130000)+*/+#define MEMMAP 0xE01FC040+#define PLLCON 0xE01FC080+#define VPBDIV 0xE01FC100+#define PLLCFG 0xE01FC084+#define PLLFEED 0xE01FC08C+#define PLLSTAT 0xE01FC088++cpu_init_crit:+	/*remap to external memory*/+	ldr r0, =0xe01fc000+	ldr	r1, =0x3+	str	r1, [r0,#0x40]+	+	/*set pll parameters*/++  ldr r1, =0x1+  str r1, [r0,#0x80]+  ++  ldr r1, =0x0+  str r1, [r0,#0x100]+  ++  ldr r1, =0x23+  str r1,[r0,#0x84]+  ++  ldr r1, =0xaa+  str r1, [r0,#0x8c]+  ldr r1, =0x55+  str r1, [r0,#0x8c]+  +  mov r1, r0+plltest_loop:+  ldrh r0,[r1,#0x88]+  tst r0,#0x400+  beq plltest_loop+  ++  ldr r0, =0x3+  str r0, [r1,#0x80]+  ++  ldr r0, =0xaa+  str r0, [r1,#0x8c]+  ldr r0, =0x55+  str r0, [r1,#0x8c]+++	mov	pc, lr+++/*************************************************/+/*	interrupt vectors	*/+/*************************************************/+real_vectors:+	b	reset+	b	undefined_instruction+	b	software_interrupt+	b	prefetch_abort+	b	data_abort+	b	not_used+	b	irq+	b	fiq++/*************************************************/++undefined_instruction:+	mov	r6, #3+	b	reset++software_interrupt:+	mov	r6, #4+	b	reset++prefetch_abort:+	mov	r6, #5+	b	reset++data_abort:+	mov	r6, #6+	b	reset++not_used:+	/* we *should* never reach this */+	mov	r6, #7+	b	reset++irq:+	mov	r6, #8+	b	reset++fiq:+	mov	r6, #9+	b	resetdiff -Naur u-boot-origin/drivers/rtl8019.c u-boot-1.1.3/drivers/rtl8019.c--- u-boot-origin/drivers/rtl8019.c	2005-09-12 12:27:52.000000000 +0800+++ u-boot-1.1.3/drivers/rtl8019.c	2005-09-07 18:23:24.000000000 +0800@@ -99,6 +99,15 @@  int eth_init (bd_t * bd) {+	+#ifdef CONFIG_LPC+	put_reg (RTL8019_COMMAND, RTL8019_PAGE3);+	put_reg (RTL8019_CR9346, 0xcf);+	put_reg (RTL8019_CONFIG3, 0x60);+	put_reg (RTL8019_CR9346, 0x0f);+	put_reg (RTL8019_COMMAND, RTL8019_PAGE0);+#endif+	 	eth_reset (); 	put_reg (RTL8019_COMMAND, RTL8019_PAGE0STOP); 	put_reg (RTL8019_DATACONFIGURATION, 0x48);diff -Naur u-boot-origin/drivers/rtl8019.h u-boot-1.1.3/drivers/rtl8019.h--- u-boot-origin/drivers/rtl8019.h	2005-09-12 12:27:52.000000000 +0800+++ u-boot-1.1.3/drivers/rtl8019.h	2005-09-07 18:28:13.000000000 +0800@@ -33,6 +33,39 @@  #ifdef CONFIG_DRIVER_RTL8019 +#ifdef CONFIG_LPC++#define   ETH_ADDR_SFT              (1)+#define   EI_SHIFT(x)               ((x)<<ETH_ADDR_SFT)+#define   RTL8019_REG_00            (RTL8019_BASE + EI_SHIFT(0x00))+#define 	RTL8019_REG_01        		(RTL8019_BASE + EI_SHIFT(0x01)) +#define 	RTL8019_REG_02        		(RTL8019_BASE + EI_SHIFT(0x02))+#define 	RTL8019_REG_03        		(RTL8019_BASE + EI_SHIFT(0x03))+#define 	RTL8019_REG_04        		(RTL8019_BASE + EI_SHIFT(0x04))+#define 	RTL8019_REG_05        		(RTL8019_BASE + EI_SHIFT(0x05))+#define 	RTL8019_REG_06        		(RTL8019_BASE + EI_SHIFT(0x06))+#define 	RTL8019_REG_07        		(RTL8019_BASE + EI_SHIFT(0x07))+#define 	RTL8019_REG_08        		(RTL8019_BASE + EI_SHIFT(0x08))+#define 	RTL8019_REG_09        		(RTL8019_BASE + EI_SHIFT(0x09))+#define 	RTL8019_REG_0a        		(RTL8019_BASE + EI_SHIFT(0x0a))+#define 	RTL8019_REG_0b        		(RTL8019_BASE + EI_SHIFT(0x0b))+#define 	RTL8019_REG_0c        		(RTL8019_BASE + EI_SHIFT(0x0c))+#define 	RTL8019_REG_0d        		(RTL8019_BASE + EI_SHIFT(0x0d))+#define 	RTL8019_REG_0e       	 	  (RTL8019_BASE + EI_SHIFT(0x0e))+#define 	RTL8019_REG_0f        		(RTL8019_BASE + EI_SHIFT(0x0f))+#define 	RTL8019_REG_10        		(RTL8019_BASE + EI_SHIFT(0x10))+#define 	RTL8019_REG_1f        		(RTL8019_BASE + EI_SHIFT(0x1f))++#define   RTL8019_CR9346    RTL8019_REG_01+#define   RTL8019_CONFIG0   RTL8019_REG_03+#define   RTL8019_CONFIG1   RTL8019_REG_04+#define   RTL8019_CONFIG2   RTL8019_REG_05+#define   RTL8019_CONFIG3   RTL8019_REG_06++#define   RTL8019_PAGE3                   0xE2++#else+ #define		RTL8019_REG_00        		(RTL8019_BASE + 0x00) #define 	RTL8019_REG_01        		(RTL8019_BASE + 0x01) #define 	RTL8019_REG_02        		(RTL8019_BASE + 0x02)@@ -52,6 +85,8 @@ #define 	RTL8019_REG_10        		(RTL8019_BASE + 0x10) #define 	RTL8019_REG_1f        		(RTL8019_BASE + 0x1f) +#endif+ #define		RTL8019_COMMAND			RTL8019_REG_00 #define		RTL8019_PAGESTART		RTL8019_REG_01 #define		RTL8019_PAGESTOP		RTL8019_REG_02diff -Naur u-boot-origin/include/asm-arm/arch-arm7tdmi/hardware.h u-boot-1.1.3/include/asm-arm/arch-arm7tdmi/hardware.h--- u-boot-origin/include/asm-arm/arch-arm7tdmi/hardware.h	1970-01-01 07:00:00.000000000 +0700+++ u-boot-1.1.3/include/asm-arm/arch-arm7tdmi/hardware.h	2005-09-07 09:44:23.000000000 +0800@@ -0,0 +1,384 @@+/********************************************************/+/*							*/+/* philihs					*/+/* lpc2294					*/+/*							*/+/********************************************************/+#ifndef __ASM_ARCH_HARDWARE_H+#define __ASM_ARCH_HARDWARE_H++/* External Memory Controller (EMC) */+#define BCFG0          (*((volatile unsigned long *) 0xFFE00000))+#define BCFG1          (*((volatile unsigned long *) 0xFFE00004))+#define BCFG2          (*((volatile unsigned long *) 0xFFE00008))+#define BCFG3          (*((volatile unsigned long *) 0xFFE0000C))++/* Vectored Interrupt Controller (VIC) */+#define VICIRQStatus   (*((volatile unsigned long *) 0xFFFFF000))+#define VICFIQStatus   (*((volatile unsigned long *) 0xFFFFF004))+#define VICRawIntr     (*((volatile unsigned long *) 0xFFFFF008))+#define VICIntSelect   (*((volatile unsigned long *) 0xFFFFF00C))+#define VICIntEnable   (*((volatile unsigned long *) 0xFFFFF010))+#define VICIntEnClr    (*((volatile unsigned long *) 0xFFFFF014))+#define VICSoftInt     (*((volatile unsigned long *) 0xFFFFF018))+#define VICSoftIntClr  (*((volatile unsigned long *) 0xFFFFF01C))+#define VICProtection  (*((volatile unsigned long *) 0xFFFFF020))+#define VICVectAddr    (*((volatile unsigned long *) 0xFFFFF030))+#define VICDefVectAddr (*((volatile unsigned long *) 0xFFFFF034))+#define VICVectAddr0   (*((volatile unsigned long *) 0xFFFFF100))+#define VICVectAddr1   (*((volatile unsigned long *) 0xFFFFF104))+#define VICVectAddr2   (*((volatile unsigned long *) 0xFFFFF108))+#define VICVectAddr3   (*((volatile unsigned long *) 0xFFFFF10C))+#define VICVectAddr4   (*((volatile unsigned long *) 0xFFFFF110))+#define VICVectAddr5   (*((volatile unsigned long *) 0xFFFFF114))+#define VICVectAddr6   (*((volatile unsigned long *) 0xFFFFF118))+#define VICVectAddr7   (*((volatile unsigned long *) 0xFFFFF11C))+#define VICVectAddr8   (*((volatile unsigned long *) 0xFFFFF120))+#define VICVectAddr9   (*((volatile unsigned long *) 0xFFFFF124))+#define VICVectAddr10  (*((volatile unsigned long *) 0xFFFFF128))+#define VICVectAddr11  (*((volatile unsigned long *) 0xFFFFF12C))+#define VICVectAddr12  (*((volatile unsigned long *) 0xFFFFF130))+#define VICVectAddr13  (*((volatile unsigned long *) 0xFFFFF134))+#define VICVectAddr14  (*((volatile unsigned long *) 0xFFFFF138))+#define VICVectAddr15  (*((volatile unsigned long *) 0xFFFFF13C))+#define VICVectCntl0   (*((volatile unsigned long *) 0xFFFFF200))+#define VICVectCntl1   (*((volatile unsigned long *) 0xFFFFF204))+#define VICVectCntl2   (*((volatile unsigned long *) 0xFFFFF208))+#define VICVectCntl3   (*((volatile unsigned long *) 0xFFFFF20C))+#define VICVectCntl4   (*((volatile unsigned long *) 0xFFFFF210))+#define VICVectCntl5   (*((volatile unsigned long *) 0xFFFFF214))+#define VICVectCntl6   (*((volatile unsigned long *) 0xFFFFF218))+#define VICVectCntl7   (*((volatile unsigned long *) 0xFFFFF21C))+#define VICVectCntl8   (*((volatile unsigned long *) 0xFFFFF220))+#define VICVectCntl9   (*((volatile unsigned long *) 0xFFFFF224))+#define VICVectCntl10  (*((volatile unsigned long *) 0xFFFFF228))+#define VICVectCntl11  (*((volatile unsigned long *) 0xFFFFF22C))+#define VICVectCntl12  (*((volatile unsigned long *) 0xFFFFF230))+#define VICVectCntl13  (*((volatile unsigned long *) 0xFFFFF234))+#define VICVectCntl14  (*((volatile unsigned long *) 0xFFFFF238))+#define VICVectCntl15  (*((volatile unsigned long *) 0xFFFFF23C))++/* Pin Connect Block */+#define PINSEL0        (*((volatile unsigned long *) 0xE002C000))+#define PINSEL1        (*((volatile unsigned long *) 0xE002C004))+#define PINSEL2        (*((volatile unsigned long *) 0xE002C014))++/* General Purpose Input/Output (GPIO) */+#define IOPIN0         (*((volatile unsigned long *) 0xE0028000))+#define IOSET0         (*((volatile unsigned long *) 0xE0028004))+#define IODIR0         (*((volatile unsigned long *) 0xE0028008))+#define IOCLR0         (*((volatile unsigned long *) 0xE002800C))+#define IOPIN1         (*((volatile unsigned long *) 0xE0028010))+#define IOSET1         (*((volatile unsigned long *) 0xE0028014))+#define IODIR1         (*((volatile unsigned long *) 0xE0028018))+#define IOCLR1         (*((volatile unsigned long *) 0xE002801C))+#define IOPIN2         (*((volatile unsigned long *) 0xE0028020))+#define IOSET2         (*((volatile unsigned long *) 0xE0028024))+#define IODIR2         (*((volatile unsigned long *) 0xE0028028))+#define IOCLR2         (*((volatile unsigned long *) 0xE002802C))+#define IOPIN3         (*((volatile unsigned long *) 0xE0028030))+#define IOSET3         (*((volatile unsigned long *) 0xE0028034))+#define IODIR3         (*((volatile unsigned long *) 0xE0028038))+#define IOCLR3         (*((volatile unsigned long *) 0xE002803C))++/* Memory Accelerator Module (MAM) */+#define MAMCR          (*((volatile unsigned char *) 0xE01FC000))+#define MAMTIM         (*((volatile unsigned char *) 0xE01FC004))+#define MEMMAP         (*((volatile unsigned char *) 0xE01FC040))++/* Phase Locked Loop (PLL) */+#define PLLCON         (*((volatile unsigned char *) 0xE01FC080))+#define PLLCFG         (*((volatile unsigned char *) 0xE01FC084))+#define PLLSTAT        (*((v