?? e_example1.vhd
字號:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity E_example1 is
port(u: in std_logic_vector(2 downto 0) ;
v: in std_logic_vector(2 downto 0) ;
w: in std_logic_vector(2 downto 0) ;
x: in std_logic_vector(2 downto 0) ;
y: in std_logic_vector(2 downto 0) ;
s: in std_logic_vector(2 downto 0) ;
Display : OUT STD_logic_vector(0 TO 6)
);
end E_example1;
ARCHITECTURE Behavior OF E_example1 IS
signal outa: std_logic_vector(2 downto 0);
COMPONENT E_multiplexer IS
port (u0 : in std_logic ;
u1 : in std_logic ;
u2 : in std_logic ;
v0 : in std_logic ;
v1 : in std_logic ;
v2 : in std_logic ;
w0 : in std_logic ;
w1 : in std_logic ;
w2 : in std_logic ;
x0 : in std_logic ;
x1 : in std_logic ;
x2 : in std_logic ;
y0 : in std_logic ;
y1 : in std_logic ;
y2 : in std_logic ;
s0 : in std_logic ;
s1 : in std_logic ;
s2 : in std_logic ;
m0 : buffer std_logic;
m1 : buffer std_logic;
m2 : buffer std_logic
);
END COMPONENT;
COMPONENT E_7_seg IS
PORT ( C : IN STD_logic_vector(2 DOWNTO 0);
Display : OUT STD_logic_vector(0 TO 6));
END COMPONENT;
BEGIN
u8: E_multiplexer PORT MAP(u(0),u(1),u(2),v(0),v(1),v(2),w(0),w(1),w(2),x(0),
x(1),x(2),y(0),y(1),y(2),s(0),s(1),s(2),outa(0),outa(1),outa(2));
u9: E_7_seg port map(outa,display);
end Behavior;
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